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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_arith.all;
- use ieee.std_logic_unsigned.all;
- entity lab4 is
- end lab4;
- architecture Behavioral of lab4 is
- COMPONENT lr4
- Port(
- clk : in std_logic;
- we : in std_logic;
- en : in std_logic;
- addr : in std_logic_vector(7 downto 0);
- di : in std_logic_vector(127 downto 0);
- do : out std_logic_vector(127 downto 0)
- );
- END COMPONENT;
- --inputs
- signal addr : std_logic_vector(7 downto 0) := (others => '0');
- signal di : std_logic_vector(127 downto 0) := (others => '0');
- signal we : std_logic := '0';
- signal en : std_logic := '1';
- signal clk : std_logic := '0';
- --outputs
- signal do : std_logic_vector(127 downto 0);
- begin
- uut: lr4 PORT MAP (
- clk => clk,
- we => we,
- en => en,
- addr => addr,
- di => di,
- do => do
- );
- gen: --генератор тактов
- process
- begin
- clk <= '0'; wait for 25 ns;
- clk <= '1'; wait for 25 ns;
- end process;
- process
- begin
- wait for 100 ns;
- en <= '1';
- we <= '1'; --write
- addr <= "00000000";
- di <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- wait for 50 ns;
- for i in 0 to 3 loop
- addr <= addr + "00000001";
- di <= di - x"00000000000000000000000000000001";
- wait for 150 ns;
- end loop;
- addr <= "00000000";
- we <= '0'; --read
- wait for 50 ns;
- for i in 0 to 3 loop
- addr <= addr + "00000001";
- wait for 150 ns;
- end loop;
- en <= '0';
- wait;
- end process;
- end Behavioral;
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