library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
entity lab81 is
    Port (clk : in std_logic;
        srst : in std_logic;
        dout : out std_logic_vector(7 downto 0));
end lab81;

architecture Behavioral of lab81 is
type ROM is array( 0 to 15) of std_logic_vector(7 downto 0);
signal cnts : ROM :=
    ( 0 => "00000000",
    1 => "00110000",
    2 => "01011001",
    3 => "01110101",
    4 => "01111111",
    5 => "01110101",
    6 => "01011001",
    7 => "00110000",
    8 => "00000000",
    9 => "11001111",
    10 => "10100110",
    11 => "10001010",
    12 => "10000001",
    13 => "10001010",
    14 => "10100110",
    15 => "11001111");
signal cntr : std_logic_vector(26 downto 0):=(others => '0');
signal s_dout : std_logic_vector(7 downto 0);
signal add : std_logic_vector(3 downto 0):=(others => '0');

begin
addres_proc : process(clk) begin
    if rising_edge(clk) then
        if srst = '1' then
            add <= (others => '0');
        else
            add <= unsigned(add) + 1;
        end if;
    end if;
end process;
gen_sin : process(clk) begin
    if rising_edge(clk) then
        s_dout <= cnts(conv_integer(unsigned(add)));
    end if;
end process;
dout <= s_dout;
end Behavioral;