xnor_vetor_sinal

library IEEE;
use ieee.std_logic_1164.all;

entity xnor_vetor_sinal is
port (a: in std_logic_vector (3 downto 0);
        saida: out std_logic);
end xnor_vetor_sinal;

architecture murrinha of xnor_vetor_sinal is
signal s: std_logic_vector (3 downto 0);
begin
s <= a xnor "1101";
saida <= s(3) and s(2) and s(1) and s(0);
end murrinha;