----------------------------------------------------------------------------------
-- Company:         LIRMM
-- Engineer: ,     Afef BOUCHAALA
--
-- Create Date:    11:16:06 04/20/2012
-- Design Name:
-- Module Name:    filtre_h3_fonction - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity filtre_h3_fonction is
       generic ( N : positive := 3;
                  m : positive :=  524288;
                    address_length_in_sig : integer := 19);
        port( add, reset_carte ,test,  clk  : in std_logic;
               -- data                      : in std_logic_vector(31 downto 0);
            test_result                 : out std_logic);
end filtre_h3_fonction;

architecture struct of filtre_h3_fonction is

component CONTROL_UNIT is
 generic (  N : positive ;
            m : positive ;
               address_length_in_sig : integer );
    Port ( reset, clk, add          : in  STD_LOGIC;
           test                     : in  STD_LOGIC;
             data                   : in  std_logic_vector (31 downto 0);
           filter_ram_out           : in  std_logic_vector ( 0 downto 0);
             test_result                : out std_logic;
           filtre_ram_enable        : out std_logic;
           filtre_ram_write_enable  : out std_logic_vector (0 downto 0);
           filtre_ram_data          : out std_logic_vector (0 downto 0);
           filtre_ram_address       : out std_logic_vector ((address_length_in_sig -1) downto 0) );
end component;



  COMPONENT filtre_ram
  PORT (
        clka    : IN STD_LOGIC;
        rsta    : IN STD_LOGIC;
        ena     : IN STD_LOGIC;
        wea     : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra : IN STD_LOGIC_VECTOR((address_length_in_sig -1) DOWNTO 0);
        dina    : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0));
    END COMPONENT;

 signal reset : std_logic;
 signal filtre_ram_enable_sig:  std_logic;
 signal filtre_ram_write_enable_sig :  std_logic_vector (0 downto 0);
 signal filtre_ram_data_sig:  std_logic_vector (0 downto 0) ;
 signal filtre_ram_address_sig : std_logic_vector((address_length_in_sig - 1)downto 0) ;
 signal filter_ram_out_sig : std_logic_vector (0 downto 0);
 signal data : std_logic_vector (31 downto 0);

 begin

 data <= "01001000000010010101101011010101";
 reset <=  not (reset_carte) ;

 CU : control_unit
 generic map ( N                        => N,
               m                        => m,
               address_length_in_sig    => address_length_in_sig )
 port map ( clk                     => clk ,
            reset                   => reset ,
            test                       => test,
            add                        => add,
            data                       => data,
            filtre_ram_enable       => filtre_ram_enable_sig,
         filtre_ram_write_enable => filtre_ram_write_enable_sig,
         filtre_ram_data        => filtre_ram_data_sig,
            filtre_ram_address  => filtre_ram_address_sig,
            test_result             => test_result,
            filter_ram_out      => filter_ram_out_sig );

fr: filtre_ram
port map (clka  => clk ,
          rsta      => reset,
          wea       => filtre_ram_write_enable_sig,
          addra     => filtre_ram_address_sig,
        dina        => filtre_ram_data_sig,
          douta     => filter_ram_out_sig,
          ena       => filtre_ram_enable_sig
          );


end struct;