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msp430x14x.h

Matt23
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  1. /******************************************************************************/
  2. /* Legacy Header File                                                         */
  3. /* Not recommended for use in new projects.                                   */
  4. /* Please use the msp430.h file or the device specific header file            */
  5. /******************************************************************************/
  6.  
  7. /********************************************************************
  8. *
  9. * Standard register and bit definitions for the Texas Instruments
  10. * MSP430 microcontroller.
  11. *
  12. * This file supports assembler and C development for
  13. * MSP430x14x devices.
  14. *
  15. * Texas Instruments, Version 2.4
  16. *
  17. * Rev. 1.2, Additional Timer B bit definitions.
  18. *           Renamed XTOFF to XT2OFF.
  19. * Rev. 1.3, Removed leading 0 to aviod interpretation as octal
  20. *            values under C
  21. * Rev. 1.4, Corrected LPMx_EXIT to reference new intrinsic _BIC_SR_IRQ
  22. *           Changed TAIV and TBIV to be read-only
  23. * Rev. 1.5, Enclose all #define statements with parentheses
  24. * Rev. 1.6, Defined vectors for USART (in addition to UART)
  25. * Rev. 1.7, Added USART special function labels (UxME, UxIE, UxIFG)
  26. * Rev. 2.1, Alignment of defintions in Users Guide and of version numbers
  27. * Rev. 2.2, Fixed type in ADC12 bit definitions (replaced ADC10 with ADC12)
  28. * Rev. 2.3, Removed unused def of TASSEL2 / TBSSEL2
  29. * Rev. 2.4, added definitions for Interrupt Vectors xxIV
  30. *
  31. ********************************************************************/
  32.  
  33. #ifndef __msp430x14x
  34. #define __msp430x14x
  35.  
  36. #define __MSP430_HEADER_VERSION__ 1059
  37.  
  38. #ifdef  __IAR_SYSTEMS_ICC__
  39. #ifndef _SYSTEM_BUILD
  40. #pragma system_include
  41. #endif
  42. #endif
  43.  
  44. #if (((__TID__ >> 8) & 0x7F) != 0x2b)     /* 0x2b = 43 dec */
  45. #error msp430x14x.h file for use with ICC430/A430 only
  46. #endif
  47.  
  48.  
  49. #ifdef __IAR_SYSTEMS_ICC__
  50. #include "in430.h"
  51. #pragma language=extended
  52.  
  53. #define DEFC(name, address) __no_init volatile unsigned char name @ address;
  54. #define DEFW(name, address) __no_init volatile unsigned short name @ address;
  55. #define DEFXC  volatile unsigned char
  56. #define DEFXW  volatile unsigned short
  57.  
  58. #endif  /* __IAR_SYSTEMS_ICC__  */
  59.  
  60.  
  61. #ifdef __IAR_SYSTEMS_ASM__
  62. #define DEFC(name, address) sfrb name = address;
  63. #define DEFW(name, address) sfrw name = address;
  64.  
  65. #endif /* __IAR_SYSTEMS_ASM__*/
  66.  
  67. #ifdef __cplusplus
  68. #define READ_ONLY
  69. #else
  70. #define READ_ONLY const
  71. #endif
  72.  
  73. /************************************************************
  74. * STANDARD BITS
  75. ************************************************************/
  76.  
  77. #define BIT0                (0x0001u)
  78. #define BIT1                (0x0002u)
  79. #define BIT2                (0x0004u)
  80. #define BIT3                (0x0008u)
  81. #define BIT4                (0x0010u)
  82. #define BIT5                (0x0020u)
  83. #define BIT6                (0x0040u)
  84. #define BIT7                (0x0080u)
  85. #define BIT8                (0x0100u)
  86. #define BIT9                (0x0200u)
  87. #define BITA                (0x0400u)
  88. #define BITB                (0x0800u)
  89. #define BITC                (0x1000u)
  90. #define BITD                (0x2000u)
  91. #define BITE                (0x4000u)
  92. #define BITF                (0x8000u)
  93.  
  94. /************************************************************
  95. * STATUS REGISTER BITS
  96. ************************************************************/
  97.  
  98. #define C                   (0x0001u)
  99. #define Z                   (0x0002u)
  100. #define N                   (0x0004u)
  101. #define V                   (0x0100u)
  102. #define GIE                 (0x0008u)
  103. #define CPUOFF              (0x0010u)
  104. #define OSCOFF              (0x0020u)
  105. #define SCG0                (0x0040u)
  106. #define SCG1                (0x0080u)
  107.  
  108. /* Low Power Modes coded with Bits 4-7 in SR */
  109.  
  110. #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
  111. #define LPM0                (CPUOFF)
  112. #define LPM1                (SCG0+CPUOFF)
  113. #define LPM2                (SCG1+CPUOFF)
  114. #define LPM3                (SCG1+SCG0+CPUOFF)
  115. #define LPM4                (SCG1+SCG0+OSCOFF+CPUOFF)
  116. /* End #defines for assembler */
  117.  
  118. #else /* Begin #defines for C */
  119. #define LPM0_bits           (CPUOFF)
  120. #define LPM1_bits           (SCG0+CPUOFF)
  121. #define LPM2_bits           (SCG1+CPUOFF)
  122. #define LPM3_bits           (SCG1+SCG0+CPUOFF)
  123. #define LPM4_bits           (SCG1+SCG0+OSCOFF+CPUOFF)
  124.  
  125. #include "in430.h"
  126.  
  127. #define LPM0      _BIS_SR(LPM0_bits)     /* Enter Low Power Mode 0 */
  128. #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
  129. #define LPM1      _BIS_SR(LPM1_bits)     /* Enter Low Power Mode 1 */
  130. #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
  131. #define LPM2      _BIS_SR(LPM2_bits)     /* Enter Low Power Mode 2 */
  132. #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
  133. #define LPM3      _BIS_SR(LPM3_bits)     /* Enter Low Power Mode 3 */
  134. #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
  135. #define LPM4      _BIS_SR(LPM4_bits)     /* Enter Low Power Mode 4 */
  136. #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
  137. #endif /* End #defines for C */
  138.  
  139. /************************************************************
  140. * PERIPHERAL FILE MAP
  141. ************************************************************/
  142.  
  143. /************************************************************
  144. * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
  145. ************************************************************/
  146.  
  147. #define IE1_                (0x0000u)  /* Interrupt Enable 1 */
  148. DEFC(   IE1               , IE1_)
  149. #define U0IE                IE1       /* UART0 Interrupt Enable Register */
  150. #define WDTIE               (0x01)
  151. #define OFIE                (0x02)
  152. #define NMIIE               (0x10)
  153. #define ACCVIE              (0x20)
  154. #define URXIE0              (0x40)
  155. #define UTXIE0              (0x80)
  156.  
  157. #define IFG1_               (0x0002u)  /* Interrupt Flag 1 */
  158. DEFC(   IFG1              , IFG1_)
  159. #define U0IFG               IFG1      /* UART0 Interrupt Flag Register */
  160. #define WDTIFG              (0x01)
  161. #define OFIFG               (0x02)
  162. #define NMIIFG              (0x10)
  163. #define URXIFG0             (0x40)
  164. #define UTXIFG0             (0x80)
  165.  
  166. #define ME1_                (0x0004u)  /* Module Enable 1 */
  167. DEFC(   ME1               , ME1_)
  168. #define U0ME                ME1      /* UART0 Module Enable Register */
  169. #define URXE0               (0x40)
  170. #define UTXE0               (0x80)
  171. #define USPIE0              (0x40)
  172.  
  173. #define IE2_                (0x0001u)  /* Interrupt Enable 2 */
  174. DEFC(   IE2               , IE2_)
  175. #define U1IE                IE2       /* UART1 Interrupt Enable Register */
  176. #define URXIE1              (0x10)
  177. #define UTXIE1              (0x20)
  178.  
  179. #define IFG2_               (0x0003u)  /* Interrupt Flag 2 */
  180. DEFC(   IFG2              , IFG2_)
  181. #define U1IFG               IFG2      /* UART1 Interrupt Flag Register */
  182. #define URXIFG1             (0x10)
  183. #define UTXIFG1             (0x20)
  184.  
  185. #define ME2_                (0x0005u)  /* Module Enable 2 */
  186. DEFC(   ME2               , ME2_)
  187. #define U1ME                ME2       /* UART1 Module Enable Register */
  188. #define URXE1               (0x10)
  189. #define UTXE1               (0x20)
  190. #define USPIE1              (0x10)
  191.  
  192. /************************************************************
  193. * WATCHDOG TIMER
  194. ************************************************************/
  195. #define __MSP430_HAS_WDT__            /* Definition to show that Module is available */
  196.  
  197. #define WDTCTL_             (0x0120u)  /* Watchdog Timer Control */
  198. DEFW(   WDTCTL            , WDTCTL_)
  199. /* The bit names have been prefixed with "WDT" */
  200. #define WDTIS0              (0x0001u)
  201. #define WDTIS1              (0x0002u)
  202. #define WDTSSEL             (0x0004u)
  203. #define WDTCNTCL            (0x0008u)
  204. #define WDTTMSEL            (0x0010u)
  205. #define WDTNMI              (0x0020u)
  206. #define WDTNMIES            (0x0040u)
  207. #define WDTHOLD             (0x0080u)
  208.  
  209. #define WDTPW               (0x5A00u)
  210.  
  211. /* WDT-interval times [1ms] coded with Bits 0-2 */
  212. /* WDT is clocked by fSMCLK (assumed 1MHz) */
  213. #define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */
  214. #define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */
  215. #define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */
  216. #define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */
  217. /* WDT is clocked by fACLK (assumed 32KHz) */
  218. #define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
  219. #define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
  220. #define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
  221. #define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */
  222. /* Watchdog mode -> reset after expired time */
  223. /* WDT is clocked by fSMCLK (assumed 1MHz) */
  224. #define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */
  225. #define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */
  226. #define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */
  227. #define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */
  228. /* WDT is clocked by fACLK (assumed 32KHz) */
  229. #define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL)                          /* 1000ms  " */
  230. #define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)                   /* 250ms   " */
  231. #define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)                   /* 16ms    " */
  232. #define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)            /* 1.9ms   " */
  233.  
  234. /* INTERRUPT CONTROL */
  235. /* These two bits are defined in the Special Function Registers */
  236. /* #define WDTIE               0x01 */
  237. /* #define WDTIFG              0x01 */
  238.  
  239. /************************************************************
  240. * HARDWARE MULTIPLIER
  241. ************************************************************/
  242. #define __MSP430_HAS_MPY__            /* Definition to show that Module is available */
  243.  
  244. #define MPY_                (0x0130u)  /* Multiply Unsigned/Operand 1 */
  245. DEFW(   MPY               , MPY_)
  246. #define MPYS_               (0x0132u)  /* Multiply Signed/Operand 1 */
  247. DEFW(   MPYS              , MPYS_)
  248. #define MAC_                (0x0134u)  /* Multiply Unsigned and Accumulate/Operand 1 */
  249. DEFW(   MAC               , MAC_)
  250. #define MACS_               (0x0136u)  /* Multiply Signed and Accumulate/Operand 1 */
  251. DEFW(   MACS              , MACS_)
  252. #define OP2_                (0x0138u)  /* Operand 2 */
  253. DEFW(   OP2               , OP2_)
  254. #define RESLO_              (0x013Au)  /* Result Low Word */
  255. DEFW(   RESLO             , RESLO_)
  256. #define RESHI_              (0x013Cu)  /* Result High Word */
  257. DEFW(   RESHI             , RESHI_)
  258. #define SUMEXT_             (0x013Eu)  /* Sum Extend */
  259. READ_ONLY DEFW( SUMEXT         , SUMEXT_)
  260.  
  261. /************************************************************
  262. * DIGITAL I/O Port1/2
  263. ************************************************************/
  264. #define __MSP430_HAS_PORT1__          /* Definition to show that Module is available */
  265. #define __MSP430_HAS_PORT2__          /* Definition to show that Module is available */
  266.  
  267. #define P1IN_               (0x0020u)  /* Port 1 Input */
  268. READ_ONLY DEFC( P1IN           , P1IN_)
  269. #define P1OUT_              (0x0021u)  /* Port 1 Output */
  270. DEFC(   P1OUT             , P1OUT_)
  271. #define P1DIR_              (0x0022u)  /* Port 1 Direction */
  272. DEFC(   P1DIR             , P1DIR_)
  273. #define P1IFG_              (0x0023u)  /* Port 1 Interrupt Flag */
  274. DEFC(   P1IFG             , P1IFG_)
  275. #define P1IES_              (0x0024u)  /* Port 1 Interrupt Edge Select */
  276. DEFC(   P1IES             , P1IES_)
  277. #define P1IE_               (0x0025u)  /* Port 1 Interrupt Enable */
  278. DEFC(   P1IE              , P1IE_)
  279. #define P1SEL_              (0x0026u)  /* Port 1 Selection */
  280. DEFC(   P1SEL             , P1SEL_)
  281.  
  282. #define P2IN_               (0x0028u)  /* Port 2 Input */
  283. READ_ONLY DEFC( P2IN           , P2IN_)
  284. #define P2OUT_              (0x0029u)  /* Port 2 Output */
  285. DEFC(   P2OUT             , P2OUT_)
  286. #define P2DIR_              (0x002Au)  /* Port 2 Direction */
  287. DEFC(   P2DIR             , P2DIR_)
  288. #define P2IFG_              (0x002Bu)  /* Port 2 Interrupt Flag */
  289. DEFC(   P2IFG             , P2IFG_)
  290. #define P2IES_              (0x002Cu)  /* Port 2 Interrupt Edge Select */
  291. DEFC(   P2IES             , P2IES_)
  292. #define P2IE_               (0x002Du)  /* Port 2 Interrupt Enable */
  293. DEFC(   P2IE              , P2IE_)
  294. #define P2SEL_              (0x002Eu)  /* Port 2 Selection */
  295. DEFC(   P2SEL             , P2SEL_)
  296.  
  297. /************************************************************
  298. * DIGITAL I/O Port3/4
  299. ************************************************************/
  300. #define __MSP430_HAS_PORT3__          /* Definition to show that Module is available */
  301. #define __MSP430_HAS_PORT4__          /* Definition to show that Module is available */
  302.  
  303. #define P3IN_               (0x0018u)  /* Port 3 Input */
  304. READ_ONLY DEFC( P3IN           , P3IN_)
  305. #define P3OUT_              (0x0019u)  /* Port 3 Output */
  306. DEFC(   P3OUT             , P3OUT_)
  307. #define P3DIR_              (0x001Au)  /* Port 3 Direction */
  308. DEFC(   P3DIR             , P3DIR_)
  309. #define P3SEL_              (0x001Bu)  /* Port 3 Selection */
  310. DEFC(   P3SEL             , P3SEL_)
  311.  
  312. #define P4IN_               (0x001Cu)  /* Port 4 Input */
  313. READ_ONLY DEFC( P4IN           , P4IN_)
  314. #define P4OUT_              (0x001Du)  /* Port 4 Output */
  315. DEFC(   P4OUT             , P4OUT_)
  316. #define P4DIR_              (0x001Eu)  /* Port 4 Direction */
  317. DEFC(   P4DIR             , P4DIR_)
  318. #define P4SEL_              (0x001Fu)  /* Port 4 Selection */
  319. DEFC(   P4SEL             , P4SEL_)
  320.  
  321. /************************************************************
  322. * DIGITAL I/O Port5/6
  323. ************************************************************/
  324. #define __MSP430_HAS_PORT5__          /* Definition to show that Module is available */
  325. #define __MSP430_HAS_PORT6__          /* Definition to show that Module is available */
  326.  
  327. #define P5IN_               (0x0030u)  /* Port 5 Input */
  328. READ_ONLY DEFC( P5IN           , P5IN_)
  329. #define P5OUT_              (0x0031u)  /* Port 5 Output */
  330. DEFC(   P5OUT             , P5OUT_)
  331. #define P5DIR_              (0x0032u)  /* Port 5 Direction */
  332. DEFC(   P5DIR             , P5DIR_)
  333. #define P5SEL_              (0x0033u)  /* Port 5 Selection */
  334. DEFC(   P5SEL             , P5SEL_)
  335.  
  336. #define P6IN_               (0x0034u)  /* Port 6 Input */
  337. READ_ONLY DEFC( P6IN           , P6IN_)
  338. #define P6OUT_              (0x0035u)  /* Port 6 Output */
  339. DEFC(   P6OUT             , P6OUT_)
  340. #define P6DIR_              (0x0036u)  /* Port 6 Direction */
  341. DEFC(   P6DIR             , P6DIR_)
  342. #define P6SEL_              (0x0037u)  /* Port 6 Selection */
  343. DEFC(   P6SEL             , P6SEL_)
  344.  
  345. /************************************************************
  346. * USART
  347. ************************************************************/
  348.  
  349. /* UxCTL */
  350. #define PENA                (0x80)        /* Parity enable */
  351. #define PEV                 (0x40)        /* Parity 0:odd / 1:even */
  352. #define SPB                 (0x20)        /* Stop Bits 0:one / 1: two */
  353. #define CHAR                (0x10)        /* Data 0:7-bits / 1:8-bits */
  354. #define LISTEN              (0x08)        /* Listen mode */
  355. #define SYNC                (0x04)        /* UART / SPI mode */
  356. #define MM                  (0x02)        /* Master Mode off/on */
  357. #define SWRST               (0x01)        /* USART Software Reset */
  358.  
  359. /* UxTCTL */
  360. #define CKPH                (0x80)        /* SPI: Clock Phase */
  361. #define CKPL                (0x40)        /* Clock Polarity */
  362. #define SSEL1               (0x20)        /* Clock Source Select 1 */
  363. #define SSEL0               (0x10)        /* Clock Source Select 0 */
  364. #define URXSE               (0x08)        /* Receive Start edge select */
  365. #define TXWAKE              (0x04)        /* TX Wake up mode */
  366. #define STC                 (0x02)        /* SPI: STC enable 0:on / 1:off */
  367. #define TXEPT               (0x01)        /* TX Buffer empty */
  368.  
  369. /* UxRCTL */
  370. #define FE                  (0x80)        /* Frame Error */
  371. #define PE                  (0x40)        /* Parity Error */
  372. #define OE                  (0x20)        /* Overrun Error */
  373. #define BRK                 (0x10)        /* Break detected */
  374. #define URXEIE              (0x08)        /* RX Error interrupt enable */
  375. #define URXWIE              (0x04)        /* RX Wake up interrupt enable */
  376. #define RXWAKE              (0x02)        /* RX Wake up detect */
  377. #define RXERR               (0x01)        /* RX Error Error */
  378.  
  379. /************************************************************
  380. * USART 0
  381. ************************************************************/
  382. #define __MSP430_HAS_UART0__          /* Definition to show that Module is available */
  383.  
  384. #define U0CTL_              (0x0070u)  /* USART 0 Control */
  385. DEFC(   U0CTL             , U0CTL_)
  386. #define U0TCTL_             (0x0071u)  /* USART 0 Transmit Control */
  387. DEFC(   U0TCTL            , U0TCTL_)
  388. #define U0RCTL_             (0x0072u)  /* USART 0 Receive Control */
  389. DEFC(   U0RCTL            , U0RCTL_)
  390. #define U0MCTL_             (0x0073u)  /* USART 0 Modulation Control */
  391. DEFC(   U0MCTL            , U0MCTL_)
  392. #define U0BR0_              (0x0074u)  /* USART 0 Baud Rate 0 */
  393. DEFC(   U0BR0             , U0BR0_)
  394. #define U0BR1_              (0x0075u)  /* USART 0 Baud Rate 1 */
  395. DEFC(   U0BR1             , U0BR1_)
  396. #define U0RXBUF_            (0x0076u)  /* USART 0 Receive Buffer */
  397. READ_ONLY DEFC( U0RXBUF        , U0RXBUF_)
  398. #define U0TXBUF_            (0x0077u)  /* USART 0 Transmit Buffer */
  399. DEFC(   U0TXBUF           , U0TXBUF_)
  400.  
  401. /* Alternate register names */
  402.  
  403. #define UCTL0               U0CTL     /* USART 0 Control */
  404. #define UTCTL0              U0TCTL    /* USART 0 Transmit Control */
  405. #define URCTL0              U0RCTL    /* USART 0 Receive Control */
  406. #define UMCTL0              U0MCTL    /* USART 0 Modulation Control */
  407. #define UBR00               U0BR0     /* USART 0 Baud Rate 0 */
  408. #define UBR10               U0BR1     /* USART 0 Baud Rate 1 */
  409. #define RXBUF0              U0RXBUF   /* USART 0 Receive Buffer */
  410. #define TXBUF0              U0TXBUF   /* USART 0 Transmit Buffer */
  411. #define UCTL0_              U0CTL_    /* USART 0 Control */
  412. #define UTCTL0_             U0TCTL_   /* USART 0 Transmit Control */
  413. #define URCTL0_             U0RCTL_   /* USART 0 Receive Control */
  414. #define UMCTL0_             U0MCTL_   /* USART 0 Modulation Control */
  415. #define UBR00_              U0BR0_    /* USART 0 Baud Rate 0 */
  416. #define UBR10_              U0BR1_    /* USART 0 Baud Rate 1 */
  417. #define RXBUF0_             U0RXBUF_  /* USART 0 Receive Buffer */
  418. #define TXBUF0_             U0TXBUF_  /* USART 0 Transmit Buffer */
  419. #define UCTL_0              U0CTL     /* USART 0 Control */
  420. #define UTCTL_0             U0TCTL    /* USART 0 Transmit Control */
  421. #define URCTL_0             U0RCTL    /* USART 0 Receive Control */
  422. #define UMCTL_0             U0MCTL    /* USART 0 Modulation Control */
  423. #define UBR0_0              U0BR0     /* USART 0 Baud Rate 0 */
  424. #define UBR1_0              U0BR1     /* USART 0 Baud Rate 1 */
  425. #define RXBUF_0             U0RXBUF   /* USART 0 Receive Buffer */
  426. #define TXBUF_0             U0TXBUF   /* USART 0 Transmit Buffer */
  427. #define UCTL_0_             U0CTL_    /* USART 0 Control */
  428. #define UTCTL_0_            U0TCTL_   /* USART 0 Transmit Control */
  429. #define URCTL_0_            U0RCTL_   /* USART 0 Receive Control */
  430. #define UMCTL_0_            U0MCTL_   /* USART 0 Modulation Control */
  431. #define UBR0_0_             U0BR0_    /* USART 0 Baud Rate 0 */
  432. #define UBR1_0_             U0BR1_    /* USART 0 Baud Rate 1 */
  433. #define RXBUF_0_            U0RXBUF_  /* USART 0 Receive Buffer */
  434. #define TXBUF_0_            U0TXBUF_  /* USART 0 Transmit Buffer */
  435.  
  436. /************************************************************
  437. * USART 1
  438. ************************************************************/
  439. #define __MSP430_HAS_UART1__          /* Definition to show that Module is available */
  440.  
  441. #define U1CTL_              (0x0078u)  /* USART 1 Control */
  442. DEFC(   U1CTL             , U1CTL_)
  443. #define U1TCTL_             (0x0079u)  /* USART 1 Transmit Control */
  444. DEFC(   U1TCTL            , U1TCTL_)
  445. #define U1RCTL_             (0x007Au)  /* USART 1 Receive Control */
  446. DEFC(   U1RCTL            , U1RCTL_)
  447. #define U1MCTL_             (0x007Bu)  /* USART 1 Modulation Control */
  448. DEFC(   U1MCTL            , U1MCTL_)
  449. #define U1BR0_              (0x007Cu)  /* USART 1 Baud Rate 0 */
  450. DEFC(   U1BR0             , U1BR0_)
  451. #define U1BR1_              (0x007Du)  /* USART 1 Baud Rate 1 */
  452. DEFC(   U1BR1             , U1BR1_)
  453. #define U1RXBUF_            (0x007Eu)  /* USART 1 Receive Buffer */
  454. READ_ONLY DEFC( U1RXBUF        , U1RXBUF_)
  455. #define U1TXBUF_            (0x007Fu)  /* USART 1 Transmit Buffer */
  456. DEFC(   U1TXBUF           , U1TXBUF_)
  457.  
  458. /* Alternate register names */
  459.  
  460. #define UCTL1               U1CTL     /* USART 1 Control */
  461. #define UTCTL1              U1TCTL    /* USART 1 Transmit Control */
  462. #define URCTL1              U1RCTL    /* USART 1 Receive Control */
  463. #define UMCTL1              U1MCTL    /* USART 1 Modulation Control */
  464. #define UBR01               U1BR0     /* USART 1 Baud Rate 0 */
  465. #define UBR11               U1BR1     /* USART 1 Baud Rate 1 */
  466. #define RXBUF1              U1RXBUF   /* USART 1 Receive Buffer */
  467. #define TXBUF1              U1TXBUF   /* USART 1 Transmit Buffer */
  468. #define UCTL1_              U1CTL_    /* USART 1 Control */
  469. #define UTCTL1_             U1TCTL_   /* USART 1 Transmit Control */
  470. #define URCTL1_             U1RCTL_   /* USART 1 Receive Control */
  471. #define UMCTL1_             U1MCTL_   /* USART 1 Modulation Control */
  472. #define UBR01_              U1BR0_    /* USART 1 Baud Rate 0 */
  473. #define UBR11_              U1BR1_    /* USART 1 Baud Rate 1 */
  474. #define RXBUF1_             U1RXBUF_  /* USART 1 Receive Buffer */
  475. #define TXBUF1_             U1TXBUF_  /* USART 1 Transmit Buffer */
  476. #define UCTL_1              U1CTL     /* USART 1 Control */
  477. #define UTCTL_1             U1TCTL    /* USART 1 Transmit Control */
  478. #define URCTL_1             U1RCTL    /* USART 1 Receive Control */
  479. #define UMCTL_1             U1MCTL    /* USART 1 Modulation Control */
  480. #define UBR0_1              U1BR0     /* USART 1 Baud Rate 0 */
  481. #define UBR1_1              U1BR1     /* USART 1 Baud Rate 1 */
  482. #define RXBUF_1             U1RXBUF   /* USART 1 Receive Buffer */
  483. #define TXBUF_1             U1TXBUF   /* USART 1 Transmit Buffer */
  484. #define UCTL_1_             U1CTL_    /* USART 1 Control */
  485. #define UTCTL_1_            U1TCTL_   /* USART 1 Transmit Control */
  486. #define URCTL_1_            U1RCTL_   /* USART 1 Receive Control */
  487. #define UMCTL_1_            U1MCTL_   /* USART 1 Modulation Control */
  488. #define UBR0_1_             U1BR0_    /* USART 1 Baud Rate 0 */
  489. #define UBR1_1_             U1BR1_    /* USART 1 Baud Rate 1 */
  490. #define RXBUF_1_            U1RXBUF_  /* USART 1 Receive Buffer */
  491. #define TXBUF_1_            U1TXBUF_  /* USART 1 Transmit Buffer */
  492.  
  493. /************************************************************
  494. * Timer A3
  495. ************************************************************/
  496. #define __MSP430_HAS_TA3__            /* Definition to show that Module is available */
  497.  
  498. #define TAIV_               (0x012Eu)  /* Timer A Interrupt Vector Word */
  499. READ_ONLY DEFW( TAIV           , TAIV_)
  500. #define TACTL_              (0x0160u)  /* Timer A Control */
  501. DEFW(   TACTL             , TACTL_)
  502. #define TACCTL0_            (0x0162u)  /* Timer A Capture/Compare Control 0 */
  503. DEFW(   TACCTL0           , TACCTL0_)
  504. #define TACCTL1_            (0x0164u)  /* Timer A Capture/Compare Control 1 */
  505. DEFW(   TACCTL1           , TACCTL1_)
  506. #define TACCTL2_            (0x0166u)  /* Timer A Capture/Compare Control 2 */
  507. DEFW(   TACCTL2           , TACCTL2_)
  508. #define TAR_                (0x0170u)  /* Timer A Counter Register */
  509. DEFW(   TAR               , TAR_)
  510. #define TACCR0_             (0x0172u)  /* Timer A Capture/Compare 0 */
  511. DEFW(   TACCR0            , TACCR0_)
  512. #define TACCR1_             (0x0174u)  /* Timer A Capture/Compare 1 */
  513. DEFW(   TACCR1            , TACCR1_)
  514. #define TACCR2_             (0x0176u)  /* Timer A Capture/Compare 2 */
  515. DEFW(   TACCR2            , TACCR2_)
  516.  
  517. /* Alternate register names */
  518. #define CCTL0               TACCTL0   /* Timer A Capture/Compare Control 0 */
  519. #define CCTL1               TACCTL1   /* Timer A Capture/Compare Control 1 */
  520. #define CCTL2               TACCTL2   /* Timer A Capture/Compare Control 2 */
  521. #define CCR0                TACCR0    /* Timer A Capture/Compare 0 */
  522. #define CCR1                TACCR1    /* Timer A Capture/Compare 1 */
  523. #define CCR2                TACCR2    /* Timer A Capture/Compare 2 */
  524. #define CCTL0_              TACCTL0_  /* Timer A Capture/Compare Control 0 */
  525. #define CCTL1_              TACCTL1_  /* Timer A Capture/Compare Control 1 */
  526. #define CCTL2_              TACCTL2_  /* Timer A Capture/Compare Control 2 */
  527. #define CCR0_               TACCR0_   /* Timer A Capture/Compare 0 */
  528. #define CCR1_               TACCR1_   /* Timer A Capture/Compare 1 */
  529. #define CCR2_               TACCR2_   /* Timer A Capture/Compare 2 */
  530. /* Alternate register names - 5xx style */
  531. #define TA0IV               TAIV      /* Timer A Interrupt Vector Word */
  532. #define TA0CTL              TACTL     /* Timer A Control */
  533. #define TA0CCTL0            TACCTL0   /* Timer A Capture/Compare Control 0 */
  534. #define TA0CCTL1            TACCTL1   /* Timer A Capture/Compare Control 1 */
  535. #define TA0CCTL2            TACCTL2   /* Timer A Capture/Compare Control 2 */
  536. #define TA0R                TAR       /* Timer A Counter Register */
  537. #define TA0CCR0             TACCR0    /* Timer A Capture/Compare 0 */
  538. #define TA0CCR1             TACCR1    /* Timer A Capture/Compare 1 */
  539. #define TA0CCR2             TACCR2    /* Timer A Capture/Compare 2 */
  540. #define TA0IV_              TAIV_     /* Timer A Interrupt Vector Word */
  541. #define TA0CTL_             TACTL_    /* Timer A Control */
  542. #define TA0CCTL0_           TACCTL0_  /* Timer A Capture/Compare Control 0 */
  543. #define TA0CCTL1_           TACCTL1_  /* Timer A Capture/Compare Control 1 */
  544. #define TA0CCTL2_           TACCTL2_  /* Timer A Capture/Compare Control 2 */
  545. #define TA0R_               TAR_      /* Timer A Counter Register */
  546. #define TA0CCR0_            TACCR0_   /* Timer A Capture/Compare 0 */
  547. #define TA0CCR1_            TACCR1_   /* Timer A Capture/Compare 1 */
  548. #define TA0CCR2_            TACCR2_   /* Timer A Capture/Compare 2 */
  549.  
  550. #define TASSEL1             (0x0200u)  /* Timer A clock source select 1 */
  551. #define TASSEL0             (0x0100u)  /* Timer A clock source select 0 */
  552. #define ID1                 (0x0080u)  /* Timer A clock input divider 1 */
  553. #define ID0                 (0x0040u)  /* Timer A clock input divider 0 */
  554. #define MC1                 (0x0020u)  /* Timer A mode control 1 */
  555. #define MC0                 (0x0010u)  /* Timer A mode control 0 */
  556. #define TACLR               (0x0004u)  /* Timer A counter clear */
  557. #define TAIE                (0x0002u)  /* Timer A counter interrupt enable */
  558. #define TAIFG               (0x0001u)  /* Timer A counter interrupt flag */
  559.  
  560. #define MC_0                (0*0x10u)  /* Timer A mode control: 0 - Stop */
  561. #define MC_1                (1*0x10u)  /* Timer A mode control: 1 - Up to CCR0 */
  562. #define MC_2                (2*0x10u)  /* Timer A mode control: 2 - Continous up */
  563. #define MC_3                (3*0x10u)  /* Timer A mode control: 3 - Up/Down */
  564. #define ID_0                (0*0x40u)  /* Timer A input divider: 0 - /1 */
  565. #define ID_1                (1*0x40u)  /* Timer A input divider: 1 - /2 */
  566. #define ID_2                (2*0x40u)  /* Timer A input divider: 2 - /4 */
  567. #define ID_3                (3*0x40u)  /* Timer A input divider: 3 - /8 */
  568. #define TASSEL_0            (0*0x100u) /* Timer A clock source select: 0 - TACLK */
  569. #define TASSEL_1            (1*0x100u) /* Timer A clock source select: 1 - ACLK  */
  570. #define TASSEL_2            (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
  571. #define TASSEL_3            (3*0x100u) /* Timer A clock source select: 3 - INCLK */
  572.  
  573. #define CM1                 (0x8000u)  /* Capture mode 1 */
  574. #define CM0                 (0x4000u)  /* Capture mode 0 */
  575. #define CCIS1               (0x2000u)  /* Capture input select 1 */
  576. #define CCIS0               (0x1000u)  /* Capture input select 0 */
  577. #define SCS                 (0x0800u)  /* Capture sychronize */
  578. #define SCCI                (0x0400u)  /* Latched capture signal (read) */
  579. #define CAP                 (0x0100u)  /* Capture mode: 1 /Compare mode : 0 */
  580. #define OUTMOD2             (0x0080u)  /* Output mode 2 */
  581. #define OUTMOD1             (0x0040u)  /* Output mode 1 */
  582. #define OUTMOD0             (0x0020u)  /* Output mode 0 */
  583. #define CCIE                (0x0010u)  /* Capture/compare interrupt enable */
  584. #define CCI                 (0x0008u)  /* Capture input signal (read) */
  585. #define OUT                 (0x0004u)  /* PWM Output signal if output mode 0 */
  586. #define COV                 (0x0002u)  /* Capture/compare overflow flag */
  587. #define CCIFG               (0x0001u)  /* Capture/compare interrupt flag */
  588.  
  589. #define OUTMOD_0            (0*0x20u)  /* PWM output mode: 0 - output only */
  590. #define OUTMOD_1            (1*0x20u)  /* PWM output mode: 1 - set */
  591. #define OUTMOD_2            (2*0x20u)  /* PWM output mode: 2 - PWM toggle/reset */
  592. #define OUTMOD_3            (3*0x20u)  /* PWM output mode: 3 - PWM set/reset */
  593. #define OUTMOD_4            (4*0x20u)  /* PWM output mode: 4 - toggle */
  594. #define OUTMOD_5            (5*0x20u)  /* PWM output mode: 5 - Reset */
  595. #define OUTMOD_6            (6*0x20u)  /* PWM output mode: 6 - PWM toggle/set */
  596. #define OUTMOD_7            (7*0x20u)  /* PWM output mode: 7 - PWM reset/set */
  597. #define CCIS_0              (0*0x1000u) /* Capture input select: 0 - CCIxA */
  598. #define CCIS_1              (1*0x1000u) /* Capture input select: 1 - CCIxB */
  599. #define CCIS_2              (2*0x1000u) /* Capture input select: 2 - GND */
  600. #define CCIS_3              (3*0x1000u) /* Capture input select: 3 - Vcc */
  601. #define CM_0                (0*0x4000u) /* Capture mode: 0 - disabled */
  602. #define CM_1                (1*0x4000u) /* Capture mode: 1 - pos. edge */
  603. #define CM_2                (2*0x4000u) /* Capture mode: 1 - neg. edge */
  604. #define CM_3                (3*0x4000u) /* Capture mode: 1 - both edges */
  605.  
  606. /* TA3IV Definitions */
  607. #define TAIV_NONE           (0x0000u)    /* No Interrupt pending */
  608. #define TAIV_TACCR1         (0x0002u)    /* TACCR1_CCIFG */
  609. #define TAIV_TACCR2         (0x0004u)    /* TACCR2_CCIFG */
  610. #define TAIV_6              (0x0006u)    /* Reserved */
  611. #define TAIV_8              (0x0008u)    /* Reserved */
  612. #define TAIV_TAIFG          (0x000Au)    /* TAIFG */
  613.  
  614. /************************************************************
  615. * Timer B7
  616. ************************************************************/
  617. #define __MSP430_HAS_TB7__            /* Definition to show that Module is available */
  618.  
  619. #define TBIV_               (0x011Eu)  /* Timer B Interrupt Vector Word */
  620. READ_ONLY DEFW( TBIV           , TBIV_)
  621. #define TBCTL_              (0x0180u)  /* Timer B Control */
  622. DEFW(   TBCTL             , TBCTL_)
  623. #define TBCCTL0_            (0x0182u)  /* Timer B Capture/Compare Control 0 */
  624. DEFW(   TBCCTL0           , TBCCTL0_)
  625. #define TBCCTL1_            (0x0184u)  /* Timer B Capture/Compare Control 1 */
  626. DEFW(   TBCCTL1           , TBCCTL1_)
  627. #define TBCCTL2_            (0x0186u)  /* Timer B Capture/Compare Control 2 */
  628. DEFW(   TBCCTL2           , TBCCTL2_)
  629. #define TBCCTL3_            (0x0188u)  /* Timer B Capture/Compare Control 3 */
  630. DEFW(   TBCCTL3           , TBCCTL3_)
  631. #define TBCCTL4_            (0x018Au)  /* Timer B Capture/Compare Control 4 */
  632. DEFW(   TBCCTL4           , TBCCTL4_)
  633. #define TBCCTL5_            (0x018Cu)  /* Timer B Capture/Compare Control 5 */
  634. DEFW(   TBCCTL5           , TBCCTL5_)
  635. #define TBCCTL6_            (0x018Eu)  /* Timer B Capture/Compare Control 6 */
  636. DEFW(   TBCCTL6           , TBCCTL6_)
  637. #define TBR_                (0x0190u)  /* Timer B Counter Register */
  638. DEFW(   TBR               , TBR_)
  639. #define TBCCR0_             (0x0192u)  /* Timer B Capture/Compare 0 */
  640. DEFW(   TBCCR0            , TBCCR0_)
  641. #define TBCCR1_             (0x0194u)  /* Timer B Capture/Compare 1 */
  642. DEFW(   TBCCR1            , TBCCR1_)
  643. #define TBCCR2_             (0x0196u)  /* Timer B Capture/Compare 2 */
  644. DEFW(   TBCCR2            , TBCCR2_)
  645. #define TBCCR3_             (0x0198u)  /* Timer B Capture/Compare 3 */
  646. DEFW(   TBCCR3            , TBCCR3_)
  647. #define TBCCR4_             (0x019Au)  /* Timer B Capture/Compare 4 */
  648. DEFW(   TBCCR4            , TBCCR4_)
  649. #define TBCCR5_             (0x019Cu)  /* Timer B Capture/Compare 5 */
  650. DEFW(   TBCCR5            , TBCCR5_)
  651. #define TBCCR6_             (0x019Eu)  /* Timer B Capture/Compare 6 */
  652. DEFW(   TBCCR6            , TBCCR6_)
  653.  
  654. /* Alternate register names - 5xx style */
  655. #define TB0IV               TBIV      /* Timer B Interrupt Vector Word */
  656. #define TB0CTL              TBCTL     /* Timer B Control */
  657. #define TB0CCTL0            TBCCTL0   /* Timer B Capture/Compare Control 0 */
  658. #define TB0CCTL1            TBCCTL1   /* Timer B Capture/Compare Control 1 */
  659. #define TB0CCTL2            TBCCTL2   /* Timer B Capture/Compare Control 2 */
  660. #define TB0CCTL3            TBCCTL3   /* Timer B Capture/Compare Control 3 */
  661. #define TB0CCTL4            TBCCTL4   /* Timer B Capture/Compare Control 4 */
  662. #define TB0CCTL5            TBCCTL5   /* Timer B Capture/Compare Control 5 */
  663. #define TB0CCTL6            TBCCTL6   /* Timer B Capture/Compare Control 6 */
  664. #define TB0R                TBR       /* Timer B Counter Register */
  665. #define TB0CCR0             TBCCR0    /* Timer B Capture/Compare 0 */
  666. #define TB0CCR1             TBCCR1    /* Timer B Capture/Compare 1 */
  667. #define TB0CCR2             TBCCR2    /* Timer B Capture/Compare 2 */
  668. #define TB0CCR3             TBCCR3    /* Timer B Capture/Compare 3 */
  669. #define TB0CCR4             TBCCR4    /* Timer B Capture/Compare 4 */
  670. #define TB0CCR5             TBCCR5    /* Timer B Capture/Compare 5 */
  671. #define TB0CCR6             TBCCR6    /* Timer B Capture/Compare 6 */
  672. #define TB0IV_              TBIV_     /* Timer B Interrupt Vector Word */
  673. #define TB0CTL_             TBCTL_    /* Timer B Control */
  674. #define TB0CCTL0_           TBCCTL0_  /* Timer B Capture/Compare Control 0 */
  675. #define TB0CCTL1_           TBCCTL1_  /* Timer B Capture/Compare Control 1 */
  676. #define TB0CCTL2_           TBCCTL2_  /* Timer B Capture/Compare Control 2 */
  677. #define TB0CCTL3_           TBCCTL3_  /* Timer B Capture/Compare Control 3 */
  678. #define TB0CCTL4_           TBCCTL4_  /* Timer B Capture/Compare Control 4 */
  679. #define TB0CCTL5_           TBCCTL5_  /* Timer B Capture/Compare Control 5 */
  680. #define TB0CCTL6_           TBCCTL6_  /* Timer B Capture/Compare Control 6 */
  681. #define TB0R_               TBR_      /* Timer B Counter Register */
  682. #define TB0CCR0_            TBCCR0_   /* Timer B Capture/Compare 0 */
  683. #define TB0CCR1_            TBCCR1_   /* Timer B Capture/Compare 1 */
  684. #define TB0CCR2_            TBCCR2_   /* Timer B Capture/Compare 2 */
  685. #define TB0CCR3_            TBCCR3_   /* Timer B Capture/Compare 3 */
  686. #define TB0CCR4_            TBCCR4_   /* Timer B Capture/Compare 4 */
  687. #define TB0CCR5_            TBCCR5_   /* Timer B Capture/Compare 5 */
  688. #define TB0CCR6_            TBCCR6_   /* Timer B Capture/Compare 6 */
  689.  
  690. #define TBCLGRP1            (0x4000u)  /* Timer B Compare latch load group 1 */
  691. #define TBCLGRP0            (0x2000u)  /* Timer B Compare latch load group 0 */
  692. #define CNTL1               (0x1000u)  /* Counter lenght 1 */
  693. #define CNTL0               (0x0800u)  /* Counter lenght 0 */
  694. #define TBSSEL1             (0x0200u)  /* Clock source 1 */
  695. #define TBSSEL0             (0x0100u)  /* Clock source 0 */
  696. #define TBCLR               (0x0004u)  /* Timer B counter clear */
  697. #define TBIE                (0x0002u)  /* Timer B interrupt enable */
  698. #define TBIFG               (0x0001u)  /* Timer B interrupt flag */
  699.  
  700. #define SHR1                (0x4000u)  /* Timer B Compare latch load group 1 */
  701. #define SHR0                (0x2000u)  /* Timer B Compare latch load group 0 */
  702.  
  703. #define TBSSEL_0            (0*0x0100u)  /* Clock Source: TBCLK */
  704. #define TBSSEL_1            (1*0x0100u)  /* Clock Source: ACLK  */
  705. #define TBSSEL_2            (2*0x0100u)  /* Clock Source: SMCLK */
  706. #define TBSSEL_3            (3*0x0100u)  /* Clock Source: INCLK */
  707. #define CNTL_0              (0*0x0800u)  /* Counter lenght: 16 bit */
  708. #define CNTL_1              (1*0x0800u)  /* Counter lenght: 12 bit */
  709. #define CNTL_2              (2*0x0800u)  /* Counter lenght: 10 bit */
  710. #define CNTL_3              (3*0x0800u)  /* Counter lenght:  8 bit */
  711. #define SHR_0               (0*0x2000u)  /* Timer B Group: 0 - individually */
  712. #define SHR_1               (1*0x2000u)  /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
  713. #define SHR_2               (2*0x2000u)  /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
  714. #define SHR_3               (3*0x2000u)  /* Timer B Group: 3 - 1 group (all) */
  715. #define TBCLGRP_0           (0*0x2000u)  /* Timer B Group: 0 - individually */
  716. #define TBCLGRP_1           (1*0x2000u)  /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
  717. #define TBCLGRP_2           (2*0x2000u)  /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
  718. #define TBCLGRP_3           (3*0x2000u)  /* Timer B Group: 3 - 1 group (all) */
  719.  
  720. /* Additional Timer B Control Register bits are defined in Timer A */
  721. #define CLLD1               (0x0400u)  /* Compare latch load source 1 */
  722. #define CLLD0               (0x0200u)  /* Compare latch load source 0 */
  723.  
  724. #define SLSHR1              (0x0400u)  /* Compare latch load source 1 */
  725. #define SLSHR0              (0x0200u)  /* Compare latch load source 0 */
  726.  
  727. #define SLSHR_0             (0*0x0200u)  /* Compare latch load sourec : 0 - immediate */
  728. #define SLSHR_1             (1*0x0200u)  /* Compare latch load sourec : 1 - TBR counts to 0 */
  729. #define SLSHR_2             (2*0x0200u)  /* Compare latch load sourec : 2 - up/down */
  730. #define SLSHR_3             (3*0x0200u)  /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
  731.  
  732. #define CLLD_0              (0*0x0200u)  /* Compare latch load sourec : 0 - immediate */
  733. #define CLLD_1              (1*0x0200u)  /* Compare latch load sourec : 1 - TBR counts to 0 */
  734. #define CLLD_2              (2*0x0200u)  /* Compare latch load sourec : 2 - up/down */
  735. #define CLLD_3              (3*0x0200u)  /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
  736.  
  737. /* TB7IV Definitions */
  738. #define TBIV_NONE           (0x0000u)    /* No Interrupt pending */
  739. #define TBIV_TBCCR1         (0x0002u)    /* TBCCR1_CCIFG */
  740. #define TBIV_TBCCR2         (0x0004u)    /* TBCCR2_CCIFG */
  741. #define TBIV_TBCCR3         (0x0006u)    /* TBCCR3_CCIFG */
  742. #define TBIV_TBCCR4         (0x0008u)    /* TBCCR4_CCIFG */
  743. #define TBIV_TBCCR5         (0x000Au)    /* TBCCR3_CCIFG */
  744. #define TBIV_TBCCR6         (0x000Cu)    /* TBCCR4_CCIFG */
  745. #define TBIV_TBIFG          (0x000Eu)    /* TBIFG */
  746.  
  747. /************************************************************
  748. * Basic Clock Module
  749. ************************************************************/
  750. #define __MSP430_HAS_BASIC_CLOCK__    /* Definition to show that Module is available */
  751.  
  752. #define DCOCTL_             (0x0056u)  /* DCO Clock Frequency Control */
  753. DEFC(   DCOCTL            , DCOCTL_)
  754. #define BCSCTL1_            (0x0057u)  /* Basic Clock System Control 1 */
  755. DEFC(   BCSCTL1           , BCSCTL1_)
  756. #define BCSCTL2_            (0x0058u)  /* Basic Clock System Control 2 */
  757. DEFC(   BCSCTL2           , BCSCTL2_)
  758.  
  759. #define MOD0                (0x01)   /* Modulation Bit 0 */
  760. #define MOD1                (0x02)   /* Modulation Bit 1 */
  761. #define MOD2                (0x04)   /* Modulation Bit 2 */
  762. #define MOD3                (0x08)   /* Modulation Bit 3 */
  763. #define MOD4                (0x10)   /* Modulation Bit 4 */
  764. #define DCO0                (0x20)   /* DCO Select Bit 0 */
  765. #define DCO1                (0x40)   /* DCO Select Bit 1 */
  766. #define DCO2                (0x80)   /* DCO Select Bit 2 */
  767.  
  768. #define RSEL0               (0x01)   /* Range Select Bit 0 */
  769. #define RSEL1               (0x02)   /* Range Select Bit 1 */
  770. #define RSEL2               (0x04)   /* Range Select Bit 2 */
  771. #define XT5V                (0x08)   /* XT5V should always be reset */
  772. #define DIVA0               (0x10)   /* ACLK Divider 0 */
  773. #define DIVA1               (0x20)   /* ACLK Divider 1 */
  774. #define XTS                 (0x40)   /* LFXTCLK 0:Low Freq. / 1: High Freq. */
  775. #define XT2OFF              (0x80)   /* Enable XT2CLK */
  776.  
  777. #define DIVA_0              (0x00)   /* ACLK Divider 0: /1 */
  778. #define DIVA_1              (0x10)   /* ACLK Divider 1: /2 */
  779. #define DIVA_2              (0x20)   /* ACLK Divider 2: /4 */
  780. #define DIVA_3              (0x30)   /* ACLK Divider 3: /8 */
  781.  
  782. #define DCOR                (0x01)   /* Enable External Resistor : 1 */
  783. #define DIVS0               (0x02)   /* SMCLK Divider 0 */
  784. #define DIVS1               (0x04)   /* SMCLK Divider 1 */
  785. #define SELS                (0x08)   /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
  786. #define DIVM0               (0x10)   /* MCLK Divider 0 */
  787. #define DIVM1               (0x20)   /* MCLK Divider 1 */
  788. #define SELM0               (0x40)   /* MCLK Source Select 0 */
  789. #define SELM1               (0x80)   /* MCLK Source Select 1 */
  790.  
  791. #define DIVS_0              (0x00)   /* SMCLK Divider 0: /1 */
  792. #define DIVS_1              (0x02)   /* SMCLK Divider 1: /2 */
  793. #define DIVS_2              (0x04)   /* SMCLK Divider 2: /4 */
  794. #define DIVS_3              (0x06)   /* SMCLK Divider 3: /8 */
  795.  
  796. #define DIVM_0              (0x00)   /* MCLK Divider 0: /1 */
  797. #define DIVM_1              (0x10)   /* MCLK Divider 1: /2 */
  798. #define DIVM_2              (0x20)   /* MCLK Divider 2: /4 */
  799. #define DIVM_3              (0x30)   /* MCLK Divider 3: /8 */
  800.  
  801. #define SELM_0              (0x00)   /* MCLK Source Select 0: DCOCLK */
  802. #define SELM_1              (0x40)   /* MCLK Source Select 1: DCOCLK */
  803. #define SELM_2              (0x80)   /* MCLK Source Select 2: XT2CLK/LFXTCLK */
  804. #define SELM_3              (0xC0)   /* MCLK Source Select 3: LFXTCLK */
  805.  
  806. /*************************************************************
  807. * Flash Memory
  808. *************************************************************/
  809. #define __MSP430_HAS_FLASH__          /* Definition to show that Module is available */
  810.  
  811. #define FCTL1_              (0x0128u)  /* FLASH Control 1 */
  812. DEFW(   FCTL1             , FCTL1_)
  813. #define FCTL2_              (0x012Au)  /* FLASH Control 2 */
  814. DEFW(   FCTL2             , FCTL2_)
  815. #define FCTL3_              (0x012Cu)  /* FLASH Control 3 */
  816. DEFW(   FCTL3             , FCTL3_)
  817.  
  818. #define FRKEY               (0x9600u)  /* Flash key returned by read */
  819. #define FWKEY               (0xA500u)  /* Flash key for write */
  820. #define FXKEY               (0x3300u)  /* for use with XOR instruction */
  821.  
  822. #define ERASE               (0x0002u)  /* Enable bit for Flash segment erase */
  823. #define MERAS               (0x0004u)  /* Enable bit for Flash mass erase */
  824. #define WRT                 (0x0040u)  /* Enable bit for Flash write */
  825. #define BLKWRT              (0x0080u)  /* Enable bit for Flash segment write */
  826. #define SEGWRT              (0x0080u)  /* old definition */ /* Enable bit for Flash segment write */
  827.  
  828. #define FN0                 (0x0001u)  /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
  829. #define FN1                 (0x0002u)  /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
  830. #ifndef FN2
  831. #define FN2                 (0x0004u)
  832. #endif
  833. #ifndef FN3
  834. #define FN3                 (0x0008u)
  835. #endif
  836. #ifndef FN4
  837. #define FN4                 (0x0010u)
  838. #endif
  839. #define FN5                 (0x0020u)
  840. #define FSSEL0              (0x0040u)  /* Flash clock select 0 */        /* to distinguish from USART SSELx */
  841. #define FSSEL1              (0x0080u)  /* Flash clock select 1 */
  842.  
  843. #define FSSEL_0             (0x0000u)  /* Flash clock select: 0 - ACLK */
  844. #define FSSEL_1             (0x0040u)  /* Flash clock select: 1 - MCLK */
  845. #define FSSEL_2             (0x0080u)  /* Flash clock select: 2 - SMCLK */
  846. #define FSSEL_3             (0x00C0u)  /* Flash clock select: 3 - SMCLK */
  847.  
  848. #define BUSY                (0x0001u)  /* Flash busy: 1 */
  849. #define KEYV                (0x0002u)  /* Flash Key violation flag */
  850. #define ACCVIFG             (0x0004u)  /* Flash Access violation flag */
  851. #define WAIT                (0x0008u)  /* Wait flag for segment write */
  852. #define LOCK                (0x0010u)  /* Lock bit: 1 - Flash is locked (read only) */
  853. #define EMEX                (0x0020u)  /* Flash Emergency Exit */
  854.  
  855. /************************************************************
  856. * Comparator A
  857. ************************************************************/
  858. #define __MSP430_HAS_COMPA__          /* Definition to show that Module is available */
  859.  
  860. #define CACTL1_             (0x0059u)  /* Comparator A Control 1 */
  861. DEFC(   CACTL1            , CACTL1_)
  862. #define CACTL2_             (0x005Au)  /* Comparator A Control 2 */
  863. DEFC(   CACTL2            , CACTL2_)
  864. #define CAPD_               (0x005Bu)  /* Comparator A Port Disable */
  865. DEFC(   CAPD              , CAPD_)
  866.  
  867. #define CAIFG               (0x01)    /* Comp. A Interrupt Flag */
  868. #define CAIE                (0x02)    /* Comp. A Interrupt Enable */
  869. #define CAIES               (0x04)    /* Comp. A Int. Edge Select: 0:rising / 1:falling */
  870. #define CAON                (0x08)    /* Comp. A enable */
  871. #define CAREF0              (0x10)    /* Comp. A Internal Reference Select 0 */
  872. #define CAREF1              (0x20)    /* Comp. A Internal Reference Select 1 */
  873. #define CARSEL              (0x40)    /* Comp. A Internal Reference Enable */
  874. #define CAEX                (0x80)    /* Comp. A Exchange Inputs */
  875.  
  876. #define CAREF_0             (0x00)    /* Comp. A Int. Ref. Select 0 : Off */
  877. #define CAREF_1             (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
  878. #define CAREF_2             (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
  879. #define CAREF_3             (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/
  880.  
  881. #define CAOUT               (0x01)    /* Comp. A Output */
  882. #define CAF                 (0x02)    /* Comp. A Enable Output Filter */
  883. #define P2CA0               (0x04)    /* Comp. A Connect External Signal to CA0 : 1 */
  884. #define P2CA1               (0x08)    /* Comp. A Connect External Signal to CA1 : 1 */
  885. #define CACTL24             (0x10)
  886. #define CACTL25             (0x20)
  887. #define CACTL26             (0x40)
  888. #define CACTL27             (0x80)
  889.  
  890. #define CAPD0               (0x01)    /* Comp. A Disable Input Buffer of Port Register .0 */
  891. #define CAPD1               (0x02)    /* Comp. A Disable Input Buffer of Port Register .1 */
  892. #define CAPD2               (0x04)    /* Comp. A Disable Input Buffer of Port Register .2 */
  893. #define CAPD3               (0x08)    /* Comp. A Disable Input Buffer of Port Register .3 */
  894. #define CAPD4               (0x10)    /* Comp. A Disable Input Buffer of Port Register .4 */
  895. #define CAPD5               (0x20)    /* Comp. A Disable Input Buffer of Port Register .5 */
  896. #define CAPD6               (0x40)    /* Comp. A Disable Input Buffer of Port Register .6 */
  897. #define CAPD7               (0x80)    /* Comp. A Disable Input Buffer of Port Register .7 */
  898.  
  899. /************************************************************
  900. * ADC12
  901. ************************************************************/
  902. #define __MSP430_HAS_ADC12__          /* Definition to show that Module is available */
  903.  
  904. #define ADC12CTL0_          (0x01A0u)  /* ADC12 Control 0 */
  905. DEFW(   ADC12CTL0         , ADC12CTL0_)
  906. #define ADC12CTL1_          (0x01A2u)  /* ADC12 Control 1 */
  907. DEFW(   ADC12CTL1         , ADC12CTL1_)
  908. #define ADC12IFG_           (0x01A4u)  /* ADC12 Interrupt Flag */
  909. DEFW(   ADC12IFG          , ADC12IFG_)
  910. #define ADC12IE_            (0x01A6u)  /* ADC12 Interrupt Enable */
  911. DEFW(   ADC12IE           , ADC12IE_)
  912. #define ADC12IV_            (0x01A8u)  /* ADC12 Interrupt Vector Word */
  913. DEFW(   ADC12IV           , ADC12IV_)
  914.  
  915. #define ADC12MEM_           (0x0140u)  /* ADC12 Conversion Memory */
  916. #ifndef __IAR_SYSTEMS_ICC__
  917. #define ADC12MEM            (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */
  918. #else
  919. #define ADC12MEM            ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
  920. #endif
  921. #define ADC12MEM0_          (0x0140u)  /* ADC12 Conversion Memory 0 */
  922. DEFW(   ADC12MEM0         , ADC12MEM0_)
  923. #define ADC12MEM1_          (0x0142u)  /* ADC12 Conversion Memory 1 */
  924. DEFW(   ADC12MEM1         , ADC12MEM1_)
  925. #define ADC12MEM2_          (0x0144u)  /* ADC12 Conversion Memory 2 */
  926. DEFW(   ADC12MEM2         , ADC12MEM2_)
  927. #define ADC12MEM3_          (0x0146u)  /* ADC12 Conversion Memory 3 */
  928. DEFW(   ADC12MEM3         , ADC12MEM3_)
  929. #define ADC12MEM4_          (0x0148u)  /* ADC12 Conversion Memory 4 */
  930. DEFW(   ADC12MEM4         , ADC12MEM4_)
  931. #define ADC12MEM5_          (0x014Au)  /* ADC12 Conversion Memory 5 */
  932. DEFW(   ADC12MEM5         , ADC12MEM5_)
  933. #define ADC12MEM6_          (0x014Cu)  /* ADC12 Conversion Memory 6 */
  934. DEFW(   ADC12MEM6         , ADC12MEM6_)
  935. #define ADC12MEM7_          (0x014Eu)  /* ADC12 Conversion Memory 7 */
  936. DEFW(   ADC12MEM7         , ADC12MEM7_)
  937. #define ADC12MEM8_          (0x0150u)  /* ADC12 Conversion Memory 8 */
  938. DEFW(   ADC12MEM8         , ADC12MEM8_)
  939. #define ADC12MEM9_          (0x0152u)  /* ADC12 Conversion Memory 9 */
  940. DEFW(   ADC12MEM9         , ADC12MEM9_)
  941. #define ADC12MEM10_         (0x0154u)  /* ADC12 Conversion Memory 10 */
  942. DEFW(   ADC12MEM10        , ADC12MEM10_)
  943. #define ADC12MEM11_         (0x0156u)  /* ADC12 Conversion Memory 11 */
  944. DEFW(   ADC12MEM11        , ADC12MEM11_)
  945. #define ADC12MEM12_         (0x0158u)  /* ADC12 Conversion Memory 12 */
  946. DEFW(   ADC12MEM12        , ADC12MEM12_)
  947. #define ADC12MEM13_         (0x015Au)  /* ADC12 Conversion Memory 13 */
  948. DEFW(   ADC12MEM13        , ADC12MEM13_)
  949. #define ADC12MEM14_         (0x015Cu)  /* ADC12 Conversion Memory 14 */
  950. DEFW(   ADC12MEM14        , ADC12MEM14_)
  951. #define ADC12MEM15_         (0x015Eu)  /* ADC12 Conversion Memory 15 */
  952. DEFW(   ADC12MEM15        , ADC12MEM15_)
  953.  
  954. #define ADC12MCTL_          (0x0080u)  /* ADC12 Memory Control */
  955. #ifndef __IAR_SYSTEMS_ICC__
  956. #define ADC12MCTL           (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */
  957. #else
  958. #define ADC12MCTL           ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
  959. #endif
  960. #define ADC12MCTL0_         (0x0080u)  /* ADC12 Memory Control 0 */
  961. DEFC(   ADC12MCTL0        , ADC12MCTL0_)
  962. #define ADC12MCTL1_         (0x0081u)  /* ADC12 Memory Control 1 */
  963. DEFC(   ADC12MCTL1        , ADC12MCTL1_)
  964. #define ADC12MCTL2_         (0x0082u)  /* ADC12 Memory Control 2 */
  965. DEFC(   ADC12MCTL2        , ADC12MCTL2_)
  966. #define ADC12MCTL3_         (0x0083u)  /* ADC12 Memory Control 3 */
  967. DEFC(   ADC12MCTL3        , ADC12MCTL3_)
  968. #define ADC12MCTL4_         (0x0084u)  /* ADC12 Memory Control 4 */
  969. DEFC(   ADC12MCTL4        , ADC12MCTL4_)
  970. #define ADC12MCTL5_         (0x0085u)  /* ADC12 Memory Control 5 */
  971. DEFC(   ADC12MCTL5        , ADC12MCTL5_)
  972. #define ADC12MCTL6_         (0x0086u)  /* ADC12 Memory Control 6 */
  973. DEFC(   ADC12MCTL6        , ADC12MCTL6_)
  974. #define ADC12MCTL7_         (0x0087u)  /* ADC12 Memory Control 7 */
  975. DEFC(   ADC12MCTL7        , ADC12MCTL7_)
  976. #define ADC12MCTL8_         (0x0088u)  /* ADC12 Memory Control 8 */
  977. DEFC(   ADC12MCTL8        , ADC12MCTL8_)
  978. #define ADC12MCTL9_         (0x0089u)  /* ADC12 Memory Control 9 */
  979. DEFC(   ADC12MCTL9        , ADC12MCTL9_)
  980. #define ADC12MCTL10_        (0x008Au)  /* ADC12 Memory Control 10 */
  981. DEFC(   ADC12MCTL10       , ADC12MCTL10_)
  982. #define ADC12MCTL11_        (0x008Bu)  /* ADC12 Memory Control 11 */
  983. DEFC(   ADC12MCTL11       , ADC12MCTL11_)
  984. #define ADC12MCTL12_        (0x008Cu)  /* ADC12 Memory Control 12 */
  985. DEFC(   ADC12MCTL12       , ADC12MCTL12_)
  986. #define ADC12MCTL13_        (0x008Du)  /* ADC12 Memory Control 13 */
  987. DEFC(   ADC12MCTL13       , ADC12MCTL13_)
  988. #define ADC12MCTL14_        (0x008Eu)  /* ADC12 Memory Control 14 */
  989. DEFC(   ADC12MCTL14       , ADC12MCTL14_)
  990. #define ADC12MCTL15_        (0x008Fu)  /* ADC12 Memory Control 15 */
  991. DEFC(   ADC12MCTL15       , ADC12MCTL15_)
  992.  
  993. /* ADC12CTL0 */
  994. #define ADC12SC             (0x001)   /* ADC12 Start Conversion */
  995. #define ENC                 (0x002)   /* ADC12 Enable Conversion */
  996. #define ADC12TOVIE          (0x004)   /* ADC12 Timer Overflow interrupt enable */
  997. #define ADC12OVIE           (0x008)   /* ADC12 Overflow interrupt enable */
  998. #define ADC12ON             (0x010)   /* ADC12 On/enable */
  999. #define REFON               (0x020)   /* ADC12 Reference on */
  1000. #define REF2_5V             (0x040)   /* ADC12 Ref 0:1.5V / 1:2.5V */
  1001. #define MSC                 (0x080)   /* ADC12 Multiple SampleConversion */
  1002. #define SHT00               (0x0100u)  /* ADC12 Sample Hold 0 Select 0 */
  1003. #define SHT01               (0x0200u)  /* ADC12 Sample Hold 0 Select 1 */
  1004. #define SHT02               (0x0400u)  /* ADC12 Sample Hold 0 Select 2 */
  1005. #define SHT03               (0x0800u)  /* ADC12 Sample Hold 0 Select 3 */
  1006. #define SHT10               (0x1000u)  /* ADC12 Sample Hold 0 Select 0 */
  1007. #define SHT11               (0x2000u)  /* ADC12 Sample Hold 1 Select 1 */
  1008. #define SHT12               (0x4000u)  /* ADC12 Sample Hold 2 Select 2 */
  1009. #define SHT13               (0x8000u)  /* ADC12 Sample Hold 3 Select 3 */
  1010. #define MSH                 (0x080)
  1011.  
  1012. #define SHT0_0               (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
  1013. #define SHT0_1               (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
  1014. #define SHT0_2               (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
  1015. #define SHT0_3               (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
  1016. #define SHT0_4               (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
  1017. #define SHT0_5               (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
  1018. #define SHT0_6               (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
  1019. #define SHT0_7               (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
  1020. #define SHT0_8               (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
  1021. #define SHT0_9               (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
  1022. #define SHT0_10             (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
  1023. #define SHT0_11             (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
  1024. #define SHT0_12             (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
  1025. #define SHT0_13             (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
  1026. #define SHT0_14             (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
  1027. #define SHT0_15             (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
  1028.  
  1029. #define SHT1_0               (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
  1030. #define SHT1_1               (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
  1031. #define SHT1_2               (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
  1032. #define SHT1_3               (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
  1033. #define SHT1_4               (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
  1034. #define SHT1_5               (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
  1035. #define SHT1_6               (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
  1036. #define SHT1_7               (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
  1037. #define SHT1_8               (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
  1038. #define SHT1_9               (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
  1039. #define SHT1_10             (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
  1040. #define SHT1_11             (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
  1041. #define SHT1_12             (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
  1042. #define SHT1_13             (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
  1043. #define SHT1_14             (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
  1044. #define SHT1_15             (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
  1045.  
  1046. /* ADC12CTL1 */
  1047. #define ADC12BUSY           (0x0001u)    /* ADC12 Busy */
  1048. #define CONSEQ0             (0x0002u)    /* ADC12 Conversion Sequence Select 0 */
  1049. #define CONSEQ1             (0x0004u)    /* ADC12 Conversion Sequence Select 1 */
  1050. #define ADC12SSEL0          (0x0008u)    /* ADC12 Clock Source Select 0 */
  1051. #define ADC12SSEL1          (0x0010u)    /* ADC12 Clock Source Select 1 */
  1052. #define ADC12DIV0           (0x0020u)    /* ADC12 Clock Divider Select 0 */
  1053. #define ADC12DIV1           (0x0040u)    /* ADC12 Clock Divider Select 1 */
  1054. #define ADC12DIV2           (0x0080u)    /* ADC12 Clock Divider Select 2 */
  1055. #define ISSH                (0x0100u)    /* ADC12 Invert Sample Hold Signal */
  1056. #define SHP                 (0x0200u)    /* ADC12 Sample/Hold Pulse Mode */
  1057. #define SHS0                (0x0400u)    /* ADC12 Sample/Hold Source 0 */
  1058. #define SHS1                (0x0800u)    /* ADC12 Sample/Hold Source 1 */
  1059. #define CSTARTADD0          (0x1000u)    /* ADC12 Conversion Start Address 0 */
  1060. #define CSTARTADD1          (0x2000u)    /* ADC12 Conversion Start Address 1 */
  1061. #define CSTARTADD2          (0x4000u)    /* ADC12 Conversion Start Address 2 */
  1062. #define CSTARTADD3          (0x8000u)    /* ADC12 Conversion Start Address 3 */
  1063.  
  1064. #define CONSEQ_0             (0*2u)      /* ADC12 Conversion Sequence Select: 0 */
  1065. #define CONSEQ_1             (1*2u)      /* ADC12 Conversion Sequence Select: 1 */
  1066. #define CONSEQ_2             (2*2u)      /* ADC12 Conversion Sequence Select: 2 */
  1067. #define CONSEQ_3             (3*2u)      /* ADC12 Conversion Sequence Select: 3 */
  1068. #define ADC12SSEL_0          (0*8u)      /* ADC12 Clock Source Select: 0 */
  1069. #define ADC12SSEL_1          (1*8u)      /* ADC12 Clock Source Select: 1 */
  1070. #define ADC12SSEL_2          (2*8u)      /* ADC12 Clock Source Select: 2 */
  1071. #define ADC12SSEL_3          (3*8u)      /* ADC12 Clock Source Select: 3 */
  1072. #define ADC12DIV_0           (0*0x20u)   /* ADC12 Clock Divider Select: 0 */
  1073. #define ADC12DIV_1           (1*0x20u)   /* ADC12 Clock Divider Select: 1 */
  1074. #define ADC12DIV_2           (2*0x20u)   /* ADC12 Clock Divider Select: 2 */
  1075. #define ADC12DIV_3           (3*0x20u)   /* ADC12 Clock Divider Select: 3 */
  1076. #define ADC12DIV_4           (4*0x20u)   /* ADC12 Clock Divider Select: 4 */
  1077. #define ADC12DIV_5           (5*0x20u)   /* ADC12 Clock Divider Select: 5 */
  1078. #define ADC12DIV_6           (6*0x20u)   /* ADC12 Clock Divider Select: 6 */
  1079. #define ADC12DIV_7           (7*0x20u)   /* ADC12 Clock Divider Select: 7 */
  1080. #define SHS_0                (0*0x400u)  /* ADC12 Sample/Hold Source: 0 */
  1081. #define SHS_1                (1*0x400u)  /* ADC12 Sample/Hold Source: 1 */
  1082. #define SHS_2                (2*0x400u)  /* ADC12 Sample/Hold Source: 2 */
  1083. #define SHS_3                (3*0x400u)  /* ADC12 Sample/Hold Source: 3 */
  1084. #define CSTARTADD_0          (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
  1085. #define CSTARTADD_1          (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
  1086. #define CSTARTADD_2          (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
  1087. #define CSTARTADD_3          (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
  1088. #define CSTARTADD_4          (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
  1089. #define CSTARTADD_5          (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
  1090. #define CSTARTADD_6          (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
  1091. #define CSTARTADD_7          (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
  1092. #define CSTARTADD_8          (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
  1093. #define CSTARTADD_9          (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
  1094. #define CSTARTADD_10        (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
  1095. #define CSTARTADD_11        (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
  1096. #define CSTARTADD_12        (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
  1097. #define CSTARTADD_13        (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
  1098. #define CSTARTADD_14        (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
  1099. #define CSTARTADD_15        (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
  1100.  
  1101. /* ADC12MCTLx */
  1102. #define INCH0               (0x0001u)    /* ADC12 Input Channel Select Bit 0 */
  1103. #define INCH1               (0x0002u)    /* ADC12 Input Channel Select Bit 1 */
  1104. #define INCH2               (0x0004u)    /* ADC12 Input Channel Select Bit 2 */
  1105. #define INCH3               (0x0008u)    /* ADC12 Input Channel Select Bit 3 */
  1106. #define SREF0               (0x0010u)    /* ADC12 Select Reference Bit 0 */
  1107. #define SREF1               (0x0020u)    /* ADC12 Select Reference Bit 1 */
  1108. #define SREF2               (0x0040u)    /* ADC12 Select Reference Bit 2 */
  1109. #define EOS                 (0x0080u)    /* ADC12 End of Sequence */
  1110.  
  1111. #define INCH_0               (0)        /* ADC12 Input Channel 0 */
  1112. #define INCH_1               (1)        /* ADC12 Input Channel 1 */
  1113. #define INCH_2               (2)        /* ADC12 Input Channel 2 */
  1114. #define INCH_3               (3)        /* ADC12 Input Channel 3 */
  1115. #define INCH_4               (4)        /* ADC12 Input Channel 4 */
  1116. #define INCH_5               (5)        /* ADC12 Input Channel 5 */
  1117. #define INCH_6               (6)        /* ADC12 Input Channel 6 */
  1118. #define INCH_7               (7)        /* ADC12 Input Channel 7 */
  1119. #define INCH_8               (8)        /* ADC12 Input Channel 8 */
  1120. #define INCH_9               (9)        /* ADC12 Input Channel 9 */
  1121. #define INCH_10             (10)        /* ADC12 Input Channel 10 */
  1122. #define INCH_11             (11)        /* ADC12 Input Channel 11 */
  1123. #define INCH_12             (12)        /* ADC12 Input Channel 12 */
  1124. #define INCH_13             (13)        /* ADC12 Input Channel 13 */
  1125. #define INCH_14             (14)        /* ADC12 Input Channel 14 */
  1126. #define INCH_15             (15)        /* ADC12 Input Channel 15 */
  1127.  
  1128. #define SREF_0               (0*0x10u)   /* ADC12 Select Reference 0 */
  1129. #define SREF_1               (1*0x10u)   /* ADC12 Select Reference 1 */
  1130. #define SREF_2               (2*0x10u)   /* ADC12 Select Reference 2 */
  1131. #define SREF_3               (3*0x10u)   /* ADC12 Select Reference 3 */
  1132. #define SREF_4               (4*0x10u)   /* ADC12 Select Reference 4 */
  1133. #define SREF_5               (5*0x10u)   /* ADC12 Select Reference 5 */
  1134. #define SREF_6               (6*0x10u)   /* ADC12 Select Reference 6 */
  1135. #define SREF_7               (7*0x10u)   /* ADC12 Select Reference 7 */
  1136.  
  1137. /* ADC12IV Definitions */
  1138. #define ADC12IV_NONE        (0x0000u)    /* No Interrupt pending */
  1139. #define ADC12IV_ADC12OVIFG  (0x0002u)    /* ADC12OVIFG */
  1140. #define ADC12IV_ADC12TOVIFG (0x0004u)    /* ADC12TOVIFG */
  1141. #define ADC12IV_ADC12IFG0   (0x0006u)    /* ADC12IFG0 */
  1142. #define ADC12IV_ADC12IFG1   (0x0008u)    /* ADC12IFG1 */
  1143. #define ADC12IV_ADC12IFG2   (0x000Au)    /* ADC12IFG2 */
  1144. #define ADC12IV_ADC12IFG3   (0x000Cu)    /* ADC12IFG3 */
  1145. #define ADC12IV_ADC12IFG4   (0x000Eu)    /* ADC12IFG4 */
  1146. #define ADC12IV_ADC12IFG5   (0x0010u)    /* ADC12IFG5 */
  1147. #define ADC12IV_ADC12IFG6   (0x0012u)    /* ADC12IFG6 */
  1148. #define ADC12IV_ADC12IFG7   (0x0014u)    /* ADC12IFG7 */
  1149. #define ADC12IV_ADC12IFG8   (0x0016u)    /* ADC12IFG8 */
  1150. #define ADC12IV_ADC12IFG9   (0x0018u)    /* ADC12IFG9 */
  1151. #define ADC12IV_ADC12IFG10  (0x001Au)    /* ADC12IFG10 */
  1152. #define ADC12IV_ADC12IFG11  (0x001Cu)    /* ADC12IFG11 */
  1153. #define ADC12IV_ADC12IFG12  (0x001Eu)    /* ADC12IFG12 */
  1154. #define ADC12IV_ADC12IFG13  (0x0020u)    /* ADC12IFG13 */
  1155. #define ADC12IV_ADC12IFG14  (0x0022u)    /* ADC12IFG14 */
  1156. #define ADC12IV_ADC12IFG15  (0x0024u)    /* ADC12IFG15 */
  1157.  
  1158. /************************************************************
  1159. * Interrupt Vectors (offset from 0xFFE0)
  1160. ************************************************************/
  1161.  
  1162. #define PORT2_VECTOR        (1 * 2u)  /* 0xFFE2 Port 2 */
  1163. #define USART1TX_VECTOR     (2 * 2u)  /* 0xFFE4 USART 1 Transmit */
  1164. #define USART1RX_VECTOR     (3 * 2u)  /* 0xFFE6 USART 1 Receive */
  1165. #define PORT1_VECTOR        (4 * 2u)  /* 0xFFE8 Port 1 */
  1166. #define TIMERA1_VECTOR      (5 * 2u)  /* 0xFFEA Timer A CC1-2, TA */
  1167. #define TIMERA0_VECTOR      (6 * 2u)  /* 0xFFEC Timer A CC0 */
  1168. #define ADC12_VECTOR          (7 * 2u)  /* 0xFFEE ADC */
  1169. #define USART0TX_VECTOR     (8 * 2u)  /* 0xFFF0 USART 0 Transmit */
  1170. #define USART0RX_VECTOR     (9 * 2u)  /* 0xFFF2 USART 0 Receive */
  1171. #define WDT_VECTOR          (10 * 2u) /* 0xFFF4 Watchdog Timer */
  1172. #define COMPARATORA_VECTOR  (11 * 2u) /* 0xFFF6 Comparator A */
  1173. #define TIMERB1_VECTOR      (12 * 2u) /* 0xFFF8 Timer B CC1-6, TB */
  1174. #define TIMERB0_VECTOR      (13 * 2u) /* 0xFFFA Timer B CC0 */
  1175. #define NMI_VECTOR          (14 * 2u) /* 0xFFFC Non-maskable */
  1176. #define RESET_VECTOR        (15 * 2u) /* 0xFFFE Reset [Highest Priority] */
  1177.  
  1178. #define UART1TX_VECTOR      USART1TX_VECTOR
  1179. #define UART1RX_VECTOR      USART1RX_VECTOR
  1180. #define UART0TX_VECTOR      USART0TX_VECTOR
  1181. #define UART0RX_VECTOR      USART0RX_VECTOR
  1182. #define ADC_VECTOR          ADC12_VECTOR
  1183.  
  1184. /************************************************************
  1185. * End of Modules
  1186. ************************************************************/
  1187. #pragma language=default
  1188.  
  1189. #endif /* #ifndef __msp430x14x */
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