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- --Lab #2: Shift_Reg_TB (Dean Nguyen)--
- --Libraries--
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- USE IEEE.NUMERIC_STD.ALL;
- --Entity--
- ENTITY Shift_Reg_TB IS
- END Shift_Reg_TB;
- --Architecture--
- ARCHITECTURE behavioral OF Shift_Reg_TB IS
- --Components--
- COMPONENT Shift_Reg
- GENERIC ( SIZE : INTEGER := 8); --Generic with default value
- PORT ( CLK, RESET_N, LOAD, SERIAL_IN : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
- SEED : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
- PARALLEL_OUT : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
- END COMPONENT;
- --Inputs--
- SIGNAL CLK_TB : STD_LOGIC := '0';
- SIGNAL RESET_N_TB : STD_LOGIC := '0';
- SIGNAL LOAD_TB : STD_LOGIC := '0';
- SIGNAL SERIAL_IN_TB : STD_LOGIC := '0';
- SIGNAL SEED_TB : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
- --Outputs--
- SIGNAL PARALLEL_OUT_TB : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
- --Constants--
- CONSTANT period : TIME := 20ns;
- BEGIN
- --Clock Process--
- clock : PROCESS
- BEGIN
- CLK_TB <= NOT CLK_TB;
- WAIT FOR period/2;
- END PROCESS;
- --Reset Process--
- reset : PROCESS
- BEGIN
- WAIT FOR 2*period;
- RESET_N_TB <= '1';
- WAIT;
- END PROCESS;
- uut: Shift_Reg
- GENERIC MAP (
- SIZE => 8)
- PORT MAP (
- CLK => CLK_TB,
- RESET_N => RESET_N_TB,
- LOAD => LOAD_TB,
- SERIAL_IN => SERIAL_IN_TB,
- SEED => SEED_TB,
- PARALLEL_OUT => PARALLEL_OUT_TB);
- stimulus : PROCESS
- BEGIN
- SEED_TB <= "00001111";
- SERIAL_IN_TB <= '1';
- RESET_N_TB <= '0';
- WAIT FOR 2*period;
- RESET_N_TB <= '1';
- LOAD_TB <= '1';
- WAIT FOR 2*period;
- FOR i IN 0 TO 9 LOOP
- LOAD_TB <= '0';
- WAIT FOR 2*period;
- END LOOP;
- END PROCESS;
- END behavioral;
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