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Shift TB - Dean Nguyen

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Sep 18th, 2018
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VHDL 1.79 KB | None | 0 0
  1. --Lab #2: Shift_Reg_TB (Dean Nguyen)--
  2.  
  3. --Libraries--
  4. LIBRARY IEEE;
  5. USE IEEE.STD_LOGIC_1164.ALL;
  6. USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  7. USE IEEE.NUMERIC_STD.ALL;
  8.  
  9. --Entity--
  10. ENTITY Shift_Reg_TB IS
  11. END Shift_Reg_TB;
  12.  
  13. --Architecture--
  14. ARCHITECTURE behavioral OF Shift_Reg_TB IS
  15.  
  16. --Components--
  17. COMPONENT Shift_Reg
  18.     GENERIC (   SIZE                                    : INTEGER   := 8); --Generic with default value
  19.     PORT        (   CLK, RESET_N, LOAD, SERIAL_IN   : IN STD_LOGIC; --Clock, reset, load, serial_in from XOR
  20.                     SEED                                    : IN STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0); --Random seed input
  21.                     PARALLEL_OUT                        : OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0)); --Output
  22. END COMPONENT;
  23.  
  24. --Inputs--
  25. SIGNAL CLK_TB           : STD_LOGIC := '0';
  26. SIGNAL RESET_N_TB       : STD_LOGIC := '0';
  27. SIGNAL LOAD_TB          : STD_LOGIC := '0';
  28. SIGNAL SERIAL_IN_TB : STD_LOGIC := '0';
  29. SIGNAL SEED_TB          : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
  30.  
  31. --Outputs--
  32. SIGNAL PARALLEL_OUT_TB  : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
  33.  
  34. --Constants--
  35. CONSTANT period     : TIME := 20ns;
  36.  
  37. BEGIN
  38.  
  39. --Clock Process--
  40. clock : PROCESS
  41.  
  42.     BEGIN
  43.    
  44.         CLK_TB <= NOT CLK_TB;
  45.         WAIT FOR period/2;
  46.        
  47.     END PROCESS;
  48.    
  49. --Reset Process--
  50. reset : PROCESS
  51.  
  52.     BEGIN
  53.    
  54.         WAIT FOR 2*period;
  55.         RESET_N_TB <= '1';
  56.         WAIT;
  57.        
  58.     END PROCESS;
  59.  
  60.     uut: Shift_Reg
  61.         GENERIC MAP (
  62.             SIZE => 8)
  63.         PORT MAP (
  64.             CLK => CLK_TB,
  65.             RESET_N => RESET_N_TB,
  66.             LOAD => LOAD_TB,
  67.             SERIAL_IN => SERIAL_IN_TB,
  68.             SEED => SEED_TB,
  69.             PARALLEL_OUT => PARALLEL_OUT_TB);
  70.        
  71.     stimulus    : PROCESS
  72.     BEGIN
  73.        
  74.         SEED_TB <= "00001111";
  75.         SERIAL_IN_TB <= '1';
  76.         RESET_N_TB <= '0';
  77.         WAIT FOR 2*period;
  78.         RESET_N_TB <= '1';
  79.         LOAD_TB <= '1';
  80.         WAIT FOR 2*period;
  81.         FOR i IN 0 TO 9 LOOP
  82.             LOAD_TB <= '0';
  83.             WAIT FOR 2*period;
  84.         END LOOP;
  85.        
  86.     END PROCESS;
  87.    
  88. END behavioral;
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