dvb_s2x_RAM.vhd

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;

entity dvb_s2x_RAM is
    Port(
        clk       : in std_logic;
        res       : in std_logic;
        WE        : in std_logic;                    -- Write enable
        address   : in integer range 0 to 64805;
        in_data   : in std_logic_vector(0 downto 0);
        out_data  : out std_logic_vector(0 downto 0));
end dvb_s2x_RAM;


architecture Behavioral of dvb_s2x_RAM is

constant C_RAM_WIDTH : integer := 1;                                            -- Specify RAM data width
constant C_RAM_DEPTH : integer := 64806;                                        -- Specify RAM depth (number of entries)

signal out_high : std_logic_vector(C_RAM_WIDTH-1 downto 0) := (others => '0');  -- RAM output data when RAM_PERFORMANCE = HIGH_PERFORMANCE
signal read_en  : std_logic := '1';                                             -- Output register enable

type ram_type is array (C_RAM_DEPTH-1 downto 0) of std_logic_vector(C_RAM_WIDTH-1 downto 0);   -- 2D Array Declaration for RAM signal

signal RAM_data : std_logic_vector(C_RAM_WIDTH-1 downto 0);
signal RAM      : ram_type := (others => (others => '0'));

begin

process(clk)
begin
    if(rising_edge(clk)) then
        if(WE = '1') then
            RAM(address) <= in_data;
        end if;
        RAM_data <= RAM(address);
    end if;
end process;


process(clk)
begin
    if(rising_edge(clk)) then
        if(res = '1') then
            out_high <= (others => '0');
        elsif(read_en = '1') then
            out_high <= RAM_data;
        end if;
    end if;
end process;
out_data <= out_high;

end Behavioral;