-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.

-- PROGRAM      "Quartus II 32-bit"
-- VERSION      "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED      "Wed Nov 15 14:46:29 2017"

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY fulldecoder IS
    PORT
    (
        enable :  IN  STD_LOGIC;
        current_state :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
        w :  OUT  STD_LOGIC_VECTOR(15 DOWNTO 0)
    );
END fulldecoder;

ARCHITECTURE bdf_type OF fulldecoder IS

COMPONENT decode
    PORT(En : IN STD_LOGIC;
         w : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         y : OUT STD_LOGIC_VECTOR(0 TO 7)
    );
END COMPONENT;

COMPONENT split
    PORT(cs : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         w3 : OUT STD_LOGIC;
         w : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
END COMPONENT;

COMPONENT combine
    PORT(o1 : IN STD_LOGIC_VECTOR(0 TO 7);
         o2 : IN STD_LOGIC_VECTOR(0 TO 7);
         w : OUT STD_LOGIC_VECTOR(0 TO 15)
    );
END COMPONENT;

SIGNAL  SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL  SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL  SYNTHESIZED_WIRE_10 :  STD_LOGIC;
SIGNAL  SYNTHESIZED_WIRE_3 :  STD_LOGIC;
SIGNAL  SYNTHESIZED_WIRE_5 :  STD_LOGIC;
SIGNAL  SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(0 TO 7);
SIGNAL  SYNTHESIZED_WIRE_8 :  STD_LOGIC_VECTOR(0 TO 7);


BEGIN



b2v_inst : decode
PORT MAP(En => SYNTHESIZED_WIRE_0,
         w => SYNTHESIZED_WIRE_9,
         y => SYNTHESIZED_WIRE_7);


b2v_inst1 : split
PORT MAP(cs => current_state,
         w3 => SYNTHESIZED_WIRE_10,
         w => SYNTHESIZED_WIRE_9);


SYNTHESIZED_WIRE_3 <= NOT(SYNTHESIZED_WIRE_10);



SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_3 AND enable;


SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_10 AND enable;


b2v_inst7 : decode
PORT MAP(En => SYNTHESIZED_WIRE_5,
         w => SYNTHESIZED_WIRE_9,
         y => SYNTHESIZED_WIRE_8);


b2v_inst8 : combine
PORT MAP(o1 => SYNTHESIZED_WIRE_7,
         o2 => SYNTHESIZED_WIRE_8,
         w => w);


END bdf_type;