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Randune1

PC_Update

Jan 12th, 2023 (edited)
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VHDL 0.91 KB | Source Code | 0 0
  1. entity PC_Update is
  2.     Port (  N : in STD_LOGIC;
  3.                 OV : in STD_LOGIC;
  4.                 Z : in STD_LOGIC;
  5.                 C : in STD_LOGIC;
  6.                 Offset : in STD_LOGIC_VECTOR(4 downto 0);
  7.                 BranchType : in STD_LOGIC_VECTOR(2 downto 0);
  8.                 Branch : in STD_LOGIC;
  9.                 PC : in  STD_LOGIC_VECTOR (5 downto 0);
  10.                 New_PC : out  STD_LOGIC_VECTOR (5 downto 0);
  11.                 CarryOUT : out STD_LOGIC);
  12. end PC_Update;
  13.  
  14. architecture Behavioral of PC_Update is
  15.     signal PC_temp : STD_LOGIC_VECTOR(5 downto 0);
  16.     signal depl : STD_LOGIC_VECTOR(5 downto 0);
  17. begin
  18.     PC_temp <= PC + 2;
  19.     depl <= Offset&"0";
  20.     New_PC <= (PC_temp + depl) when (Branch = '1' and ((BranchType = b"011" and N = '1')
  21.                                                                 or (BranchType = b"000" and OV = '1')
  22.                                                                 or (BranchType = b"010" and Z = '1')
  23.                                                                 or (BranchType = b"001" and C = '1')
  24.                                                                 or (BranchType = b"111"))) else
  25.                 PC_temp;
  26.     CarryOUT <= C;
  27.  
  28. end Behavioral;
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