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- entity comp_egalitate_1_bit is
- port(A,B: in BIT;
- Y: out BIT);
- end comp_egalitate_1_bit;
- architecture arh of comp_egalitate_1_bit is
- component poarta_xnor
- port(A,B: in BIT;
- C: out BIT);
- end component poarta_xnor;
- begin
- C1: poarta_xnor port map(A,B,Y);
- end arh;
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