flipflop_D

library ieee;
use ieee.std_logic_1164.all;

entity flipflop is
port (d, clk: in STD_LOGIC;
      q: out  STD_LOGIC);
end flipflop;

architecture behavioral of flipflop is
begin
    process (clk)
    begin
        if clk'event and clk = '1' then
        q <= d;
        end if ;
    end process;
end behavioral;