usi2h.asm Rx and Tx both seem to work at 600baud

.include "tn85def.inc" ;usi2h:  Want to tidy up usiTx into one call. Done
;fixed some problems. The Rx was interfeering with the next tx so I've made the Tx pin (PB1)
; an input unless it's actually just about to transmit then it's an output
again:
       ldi r16, low(RAMEND)
        out SPL, r16
        ldi r16,high(RAMEND)
        out SPH, r16
;rjmp split62
;ldi r17,17
;ldi r18,18
;ldi r16,$a6
;rcall split62
;nop
;rcall reverseBits
;ag1:
;rjmp ag1
		ldi r16,$ff
		out DDRB,r16
		out PORTB,r16
		ldi r19,(1<<USIWM0)|(0<<USICS0) ;need this otherwise msb not initially joined to D0
    	out USICR,r19
;rjmp test_usiTx
rjmp test_usiRx0

ldi r16,$a7 ;!!<--- this works. Comes out as $a6, after reversing and splitiing, on terminal at about 1Hz
rcall reverseBits
rcall split62
		rcall SPITransfer_Fast2
		mov r16,r17
		rcall SPITransfer_Fast2
		rjmp here



		ldi r16,$a5
		rcall SPITransfer_Fast2
		ldi r16,$bf
		rcall SPITransfer_Fast2

		;rcall SPITransfer
here:
rcall oneSec
rcall oneSec
rcall oneSec
rjmp again



;-----------------------------------
SPITransfer_Fast2:
out USIDR,r16
;fin2:
;rjmp fin2
;ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
ldi r19,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
ldi r18,8
upt2:
;out USICR,r16 ; MSB
rcall oneBitTime
;rcall oneSec
;rjmp upt2
out USICR,r19
up3:
;rjmp up3
dec r18
brne upt2

ret
;---------------------------------------

halfBitTime:    ;better name for this delay. Half of 1/600
;myDelay1200:
;ldi r21,13 ; 13 works for m328 at 16Mhz
push r20
push r21
ldi r21,7       ;try 7 for tiny85 at 8Hmz
ldi r20,130     ;r20,21 at 130,7 give 833uS. Good for 600baud at 8Mhz
starthbt:
 inc r20
 nop
 brne starthbt
 dec r21
 brne starthbt
 pop r21
 pop r20
 ret
;--------------------------------------------------
oneBitTime:
        rcall halfBitTime
        rcall halfBitTime
ret
;---------------------------------
delay100ms:	;handy; delay for about 0.1 sec = 100 ms
;header endif_1,10,"delay100ms"
;delay100ms:
;.ifdef testing
;	ldi r16,1
;.else
push r16
	ldi r16,60
.;endif
upd100:
	rcall oneBitTime
	dec r16
	brne upd100
pop r16
ret	;after about a tenth of a second
;------------------------
oneSec:
;jmp finsec		;take out when not simulating
push r17
ldi r17,5
upones:
	rcall delay100ms
	dec r17
	brne upones
	pop r17
finsec:
ret
;-----------------------------------
reverseBits:	;r16 gets reversed
push r17
push r18
ldi r18,8
;ldi r16,$a6
ldi r17,0
uprb:

lsl r16
ror r17
dec r18
brne uprb
uprb2:
mov r16,r17
pop r18
pop r17
ret
;-----------------------
split62:		;split r16 into two bytes, r16 and r17 where r16 contains first 6 bits preceded by
; by 10, the last stop bit then start bit. Last two bits go into r17 followed by 6 1's. ie 6 stop bits.
;ldi r16,$f0. Wrecks r16,17
ldi r17,$ff
clc
ror r16
ror r17
sec
ror r16
ror r17
ret
rjmp split62
;-----------------------------------
usiTx: ;this is going to be THE tx routine for usi tx. Assume byte to be transferred is in r16
	ldi r17,$fe		;make r1 an output as this stage. Can interfere with Rx
	out DDRB,r17

		rcall reverseBits		;needed
		rcall split62			;now have (10 + 6lsbs) + (2 msbs + 6Stops) in r116,r17
		rcall SPITransfer_Fast2	;there's the r16 gone
		mov r16,r17
		rcall SPITransfer_Fast2	;and the r17.
ret		;with r16 having been sent via USI Tx
;-------------------------------------------
test_usiTx:		;works
ldi r16,$61
rcall usiTx
ldi r16, $62
rcall usiTx
rcall oneSec
rjmp test_usiTx
;--------------------------------------------------------


usiRx0:		;try this for usi rx
;make PB0 = D0 an input
ldi r16,$fc
out DDRB,r16
ldi r16,$ff
out PORTB,r16
out USIDR,r16	;fill up usidr with only stop bits. Gruadually push them out by inpit bits
;ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

rcall waitForPin0High
rcall waitForPin0Low
rcall halfBitTime	;go to middle of start bit then..
rcall oneBitTime	;go to middle of first real bit
ldi r18,8
;out USICR,r16 ; MSB
get1bit:
out USICR,r17
rcall oneBitTime
dec r18
brne get1bit
rjmp fin

out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16 ; LSB
out USICR,r17
fin:
in r16,USIDR
		rcall reverseBits		;needed

ret
;---------------------
test_usiRx0:
	rcall usiRx0
;	rcall oneSec
;	ldi r17,$fe		;make r1 an output as this stage
;	out DDRB,r17
	rcall usiTx	;print what we found coming in
;	rcall oneSec
	rjmp test_usiRx0
;--------------------------------
waitForPin0Low:
;	ldi zl,0x36
;	clr zh
;	ld r16,z
	;rcall d16
;	rcall spacecode
	sbic PINB,0
	rjmp waitForPin0Low
ret	;when pin PB1 goes low
;------------------------

waitForPin0High:
	sbis PINB,0
	rjmp waitForPin0High
ret	;when pin PB1 goes high