VHDL_Assingment

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;


entity assignment is


  Port (
        A,B,Sel : in STD_LOGIC_VECTOR (3 downto 0);
        Y : inout STD_LOGIC_VECTOR (3 downto 0);
        zero,comp : out STD_LOGIC_VECTOR (3 downto 0));
end entity;


architecture System1 of assignment is


begin

    my_process : process (A,B,Sel)
    begin
        case (Sel) is
 -------------------------- ID:-170105036 ---------------------

            when "0000" => Y <= A;--0
            when "0001" => Y <= B;--1
            when "0011" => Y <= A or B;--3
            when "0101" => Y <= A nor B;--5
            when "0110" => Y <= A xor B;--6
            when "0111" => Y <= A xnor B;--7
            when others => Y <= x"0";--otherwise

        end case;
    end process my_process;


    State_Flag : process (A,B,Y)
    begin

        if (Y = "0000") then
            zero <= x"1";
        else
            zero <= x"0";
        end if;


        if (A > B) then
            comp <= x"1";
        else
            comp <= x"0";
        end if;

    end process;
end architecture;