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ckroy

VHDL_Assingment

Mar 27th, 2021
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.numeric_std.all;
  4. USE IEEE.std_logic_arith.all;
  5. USE IEEE.std_logic_unsigned.all;
  6.  
  7.  
  8. entity assignment is
  9.  
  10.  
  11.   Port (
  12.         A,B,Sel : in STD_LOGIC_VECTOR (3 downto 0);
  13.         Y : inout STD_LOGIC_VECTOR (3 downto 0);
  14.         zero,comp : out STD_LOGIC_VECTOR (3 downto 0));
  15. end entity;
  16.  
  17.  
  18. architecture System1 of assignment is
  19.  
  20.  
  21. begin
  22.    
  23.     my_process : process (A,B,Sel)
  24.     begin
  25.         case (Sel) is
  26.  -------------------------- ID:-170105036 ---------------------      
  27.            
  28.             when "0000" => Y <= A;--0
  29.             when "0001" => Y <= B;--1
  30.             when "0011" => Y <= A or B;--3
  31.             when "0101" => Y <= A nor B;--5
  32.             when "0110" => Y <= A xor B;--6
  33.             when "0111" => Y <= A xnor B;--7
  34.             when others => Y <= x"0";--otherwise
  35.        
  36.         end case;
  37.     end process my_process;
  38.    
  39.    
  40.     State_Flag : process (A,B,Y)
  41.     begin
  42.  
  43.         if (Y = "0000") then
  44.             zero <= x"1";
  45.         else
  46.             zero <= x"0";
  47.         end if;
  48.  
  49.        
  50.         if (A > B) then
  51.             comp <= x"1";
  52.         else
  53.             comp <= x"0";
  54.         end if;
  55.            
  56.     end process;
  57. end architecture;
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