library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AssociativeMemory is
    Port (
        clk       : in  STD_LOGIC;
        we        : in  STD_LOGIC;
        am_addr      : in  STD_LOGIC_VECTOR(15 downto 0);  -- 13 Bit für 8192+ Einträge
        am_data_in   : in  STD_LOGIC_VECTOR(31 downto 0);
        am_data_out  : out STD_LOGIC_VECTOR(31 downto 0)
    );
end AssociativeMemory;

architecture Behavioral of AssociativeMemory is
    constant VECTOR_WIDTH   : integer := 10000;
    constant WORD_WIDTH     : integer := 32;
    constant NUM_VECTORS    : integer := 5;
    constant CHUNKS_PER_VEC : integer := (VECTOR_WIDTH + WORD_WIDTH - 1) / WORD_WIDTH;  -- 313
    constant MEM_DEPTH      : integer := CHUNKS_PER_VEC * NUM_VECTORS;  -- 32 * 313 = 10016

    type memory_array is array (0 to MEM_DEPTH - 1) of std_logic_vector(WORD_WIDTH - 1 downto 0);
    signal memory : memory_array := (others => (others => '0'));

    attribute ram_style : string;
    attribute ram_style of memory : signal is "block";
begin
    process(clk)
    variable addr_int : integer;
    begin
        if rising_edge(clk) then
            addr_int := to_integer(unsigned(am_addr));
            if addr_int < MEM_DEPTH then
                if we = '1' then
                    memory(addr_int) <= am_data_in;
                end if;
                am_data_out <= memory(addr_int);
            else
                report "Invalid memory access at addr = " & integer'image(addr_int)
                    severity failure;
                am_data_out <= (others => '0'); -- Fallback
            end if;
        end if;
    end process;

end Behavioral;