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-- Company:
-- Engineer:
--
-- Create Date:    11:14:47 05/17/2019
-- Design Name:
-- Module Name:    entita_a - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity entita_a is
    Port ( CLK : in  STD_LOGIC;
           SDATA : in  STD_LOGIC := '0';
           R_W_neg : in  STD_LOGIC;
           EN : in  STD_LOGIC;
           DATA_OUT : out  STD_LOGIC);
end entita_a;

architecture Behavioral of entita_a is
type ram_display is array (15 downto 0) of std_logic_vector (15 downto 0);
signal display: ram_display;
signal address : std_logic_vector (3 downto 0);
signal flag_lettura_indirizzo, cnt : integer := 0;
signal buffer_scrittura, buffer_lettura : std_logic_vector (15 downto 0);
signal tmp_out : std_logic;
begin

    process (CLK)
        begin
            if rising_edge(CLK) then
                if flag_lettura_indirizzo = 0 then
                    if cnt > 3 then
                        flag_lettura_indirizzo <= 1;
                        cnt <= 0;
                    else
                        address <= address(2 downto 0) & SDATA;
                        cnt <= cnt +1;
                    end if;
                else
                    if (R_W_neg = '0') then
                        if cnt < 16 then
                            buffer_scrittura <= buffer_scrittura(14 downto 0) & SDATA;
                            cnt <= cnt +1;
                        else
                            display(conv_integer(address)) <= buffer_scrittura;
                            cnt <= 0;
                            flag_lettura_indirizzo <= 0;
                        end if;
                    else
                        if cnt = 0 then
                            buffer_lettura <= display(conv_integer(address));
                            cnt <= cnt +1;
                        elsif cnt < 17 then
                            tmp_out <= buffer_lettura(15);
                            buffer_lettura <= buffer_lettura(14 downto 0) & buffer_lettura(15);
                            cnt <= cnt + 1;
                        else
                            tmp_out <= 'Z';
                            cnt <= 0;
                            flag_lettura_indirizzo <= 0;
                        end if;
                    end if;

                end if;
            end if;
        end process;

DATA_OUT <= tmp_out when EN = '1' else
                'Z';
end Behavioral;