cursofpgavhdl

display_vetores

Dec 10th, 2019
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VHDL 1.10 KB | None | 0 0
  1. -- Decodificador BCD para 7 segmentos (vetores)
  2. -- Entrada: bcd (vetor de 4 posicoes);
  3. -- Saida: HEX (vetor de 7 posicoes)
  4. -- Autores: Joao Vitor e Marcos Meira
  5. -- 29/07/2017
  6.  
  7. library ieee;
  8. use ieee.std_logic_1164.all;
  9. use ieee.std_logic_unsigned.all;
  10.  
  11. entity display_vetores is
  12. port(bcd: in std_logic_vector (3 downto 0);
  13.       HEX0: out std_logic_vector (0 to 6));
  14. end display_vetores;
  15.  
  16. architecture arquitetura of display_vetores is
  17. begin
  18.     process(bcd)
  19.     begin  
  20.         case bcd is
  21.             when "0000" => HEX0 <= NOT "1111110";
  22.             when "0001" => HEX0 <= NOT "0110000";
  23.             when "0010" => HEX0 <= NOT "1101101";
  24.             when "0011" => HEX0 <= NOT "1111001";
  25.             when "0100" => HEX0 <= NOT "0110011";
  26.             when "0101" => HEX0 <= NOT "1011011";
  27.             when "0110" => HEX0 <= NOT "1011111";
  28.             when "0111" => HEX0 <= NOT "1110000";
  29.             when "1000" => HEX0 <= NOT "1111111";
  30.             when "1001" => HEX0 <= NOT "1110011";
  31.             when others => HEX0 <= NOT "0000000";
  32.         end case;
  33.     end process;
  34. end arquitetura;
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