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sreejith2904

tnkernel_startup_gcc.s

Mar 12th, 2011
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  1. /*-----------------------------------------------------------------------------
  2. //
  3. //    TNKernel startup file  for ARM processors(running from FLASH)
  4. //
  5. //
  6. // Copyright © 2004,2005 Yuri Tiomkin
  7. // All rights reserved.
  8. //
  9. // Permission to use, copy, modify, and distribute this software in source
  10. // and binary forms and its documentation for any purpose and without fee
  11. // is hereby granted, provided that the above copyright notice appear
  12. // in all copies and that both that copyright notice and this permission
  13. // notice appear in supporting documentation.
  14. //
  15. // THIS SOFTWARE IS PROVIDED BY THE YURI TIOMKIN AND CONTRIBUTORS ``AS IS'' AND
  16. // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18. // ARE DISCLAIMED. IN NO EVENT SHALL YURI TIOMKIN OR CONTRIBUTORS BE LIABLE
  19. // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20. // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21. // OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22. // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23. // LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24. // OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25. // SUCH DAMAGE.
  26. //-----------------------------------------------------------------------------*/
  27.  
  28.  
  29.     .equ MODE_BITS,   0x1F               /* Bit mask for mode bits in CPSR */
  30.     .equ USR_MODE,    0x10               /* User mode */
  31.     .equ FIQ_MODE,    0x11               /* Fast Interrupt Request mode */
  32.     .equ IRQ_MODE,    0x12               /* Interrupt Request mode */
  33.     .equ SVC_MODE,    0x13               /* Supervisor mode */
  34.     .equ ABT_MODE,    0x17               /* Abort mode */
  35.     .equ UND_MODE,    0x1B               /* Undefined Instruction mode */
  36.     .equ SYS_MODE,    0x1F               /* System mode */
  37.  
  38.  
  39.     .section    .reset, "ax"
  40.     .global  __reset
  41.     .global  __main
  42.     .code 32
  43.  
  44. __main:
  45. __reset:
  46.         ldr  pc, reset_handler_address
  47.         ldr  pc, undef_handler_address
  48.         ldr  pc, swi_handler_address
  49.         ldr  pc, pabort_handler_address
  50.         ldr  pc, dabort_handler_address
  51.              .word  0xB8A06F58                  /* 0 - (sum of other vectors instructions) */
  52.         ldr  pc, irq_handler_address
  53.         ldr  pc, fiq_handler_address
  54.  
  55. reset_handler_address:   .word  reset_handler
  56. undef_handler_address:   .word  undef_handler
  57. swi_handler_address:     .word  swi_handler
  58. pabort_handler_address:  .word  pabort_handler
  59. dabort_handler_address:  .word  dabort_handler
  60.                          .word   0x00
  61. irq_handler_address:     .word  tn_cpu_irq_isr
  62. fiq_handler_address:     .word  tn_cpu_fiq_isr
  63.    
  64.  
  65.     .text
  66.     .code 32
  67.     .align 0
  68.  
  69. reset_handler:
  70.         b  _start
  71. undef_handler:
  72.         b  undef_handler
  73. swi_handler:
  74.         b  swi_handler
  75. pabort_handler:
  76.         b  pabort_handler
  77. dabort_handler:
  78.         b  dabort_handler
  79. tn_cpu_irq_isr:
  80.     b tn_cpu_irq_isr
  81. tn_cpu_fiq_isr:
  82.     b tn_cpu_fiq_isr
  83.    
  84.  
  85.  /*--- Start */
  86.  
  87.         .extern  tn_startup_hardware_init
  88.  
  89. _start:
  90.         ldr    r0,=tn_startup_hardware_init      /* vital hardware init */
  91.         mov    lr,pc
  92.         bx     r0
  93.  
  94.     /*---- init stacks */
  95.  
  96.         mrs    r0,cpsr                           /* Original PSR value */
  97.  
  98.         bic    r0,r0,#MODE_BITS                  /* Clear the mode bits */
  99.         orr    r0,r0,#IRQ_MODE                   /* Set IRQ mode bits */
  100.         msr    cpsr_c,r0                         /* Change the mode */
  101.         ldr    sp, stack_irq_end                 /* End of IRQ_STACK */
  102.  
  103.         bic    r0,r0,#MODE_BITS                  /* Clear the mode bits */
  104.         orr    r0,r0,#FIQ_MODE                   /* Set FIQ mode bits */
  105.         msr    cpsr_c,r0                         /* Change the mode   */
  106.         ldr    sp, stack_fiq_end                 /* End of FIQ_STACK  */
  107.  
  108.         bic    r0,r0,#MODE_BITS                  /* Clear the mode bits */
  109.         orr    r0,r0,#SVC_MODE                   /* Set Supervisor mode bits */
  110.         msr    cpsr_c,r0                         /* Change the mode */
  111.         ldr    sp, stack_end                     /* End of stack */
  112.  
  113.         /*-- Leave core in SVC mode ! */
  114.  
  115.  
  116.  .extern     __bss_start
  117.  .extern     __bss_end__
  118.  
  119.      /* ----- Clear BSS (zero init) */
  120.  
  121.         mov   r0,#0
  122.         ldr   r1,=__bss_start
  123.         ldr   r2,=__bss_end__
  124. 2:      cmp   r1,r2
  125.         strlo r0,[r1],#4
  126.         blo   2b
  127.  
  128.  
  129.     /*---- Copy Initialized data from FLASH to RAM */
  130.  
  131.  .extern  _etext
  132.  .extern  _data
  133.  .extern  _edata
  134.  
  135.         ldr   r1,=_etext
  136.         ldr   r2,=_data
  137.         ldr   r3,=_edata
  138. 1:      cmp   r2,r3
  139.         ldrlo r0,[r1],#4
  140.         strlo r0,[r2],#4
  141.         blo   1b
  142.  
  143.  
  144.    /*----  */
  145.  
  146.         .extern   main
  147.  
  148.         ldr    r0,=main
  149.         mov    pc, r0                        /*  goto main() */
  150.  
  151.         /*--- Return from main -> loop forever. */
  152.  
  153. exit_loop:
  154.  
  155.         b      exit_loop
  156. /*--------------------------  */
  157.   .extern   __stack_irq_bottom_end__
  158.   .extern   __stack_fiq_bottom_end__
  159.   .extern   __stack_bottom_end__
  160.  
  161. stack_end:      .word   __stack_irq_bottom_end__
  162. stack_irq_end:  .word   __stack_fiq_bottom_end__
  163. stack_fiq_end:  .word   __stack_bottom_end__
  164.  
  165. /*-----------------------------------------------------------------------------*/
  166. /*-----------------------------------------------------------------------------*/
  167. /*-----------------------------------------------------------------------------*/
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