lima: enable shader GP debug
=======================================================
    glmark2 2017.07
=======================================================
    OpenGL Information
    GL_VENDOR:     lima
    GL_RENDERER:   Mali400
    GL_VERSION:    OpenGL ES 2.0 Mesa 18.2.0-rc5 (git-a099ba07c3)
=======================================================
[build] use-vbo=false:shader: MESA_SHADER_VERTEX
name: GLSL1
inputs: 1
outputs: 5
uniforms: 4
shared: 0
decl_var uniform INTERP_MODE_NONE mat4 ModelViewProjectionMatrix (0, 0, 0)
decl_var shader_in INTERP_MODE_NONE vec3 position (VERT_ATTRIB_GENERIC0.xyz, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 gl_Position (VARYING_SLOT_POS, 0, 0)
decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.x, 1, 0)
decl_var shader_out INTERP_MODE_NONE float Color@0 (VARYING_SLOT_VAR9.y, 1, 0)
decl_var shader_out INTERP_MODE_NONE float Color@1 (VARYING_SLOT_VAR9.z, 1, 0)
decl_var shader_out INTERP_MODE_NONE float Color@2 (VARYING_SLOT_VAR9.w, 1, 0)
decl_function main (0 params)

impl main {
	block block_0:
	/* preds: */
	vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
	vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0) /* base=0 */ /* component=0 */	/* position */
	vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1) /* base=0 */ /* component=1 */
	vec1 32 ssa_3 = intrinsic load_input (ssa_0) (0, 2) /* base=0 */ /* component=2 */
	vec1 32 ssa_4 = load_const (0x3f000000 /* 0.500000 */)
	vec1 32 ssa_5 = load_const (0x3f666666 /* 0.900000 */)
	vec1 32 ssa_6 = sne ssa_1, ssa_4
	vec1 32 ssa_7 = fnot ssa_6
	vec1 32 ssa_8 = bcsel ssa_7, ssa_0, ssa_5
	vec1 32 ssa_9 = bcsel ssa_7, ssa_5, ssa_0
	vec1 32 ssa_10 = load_const (0x3f800000 /* 1.000000 */)
	vec1 32 ssa_11 = intrinsic load_uniform (ssa_0) (0, 4, 0) /* base=0 */ /* range=4 */ /* component=0 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_12 = intrinsic load_uniform (ssa_0) (0, 4, 1) /* base=0 */ /* range=4 */ /* component=1 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_13 = intrinsic load_uniform (ssa_0) (0, 4, 2) /* base=0 */ /* range=4 */ /* component=2 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_14 = intrinsic load_uniform (ssa_0) (0, 4, 3) /* base=0 */ /* range=4 */ /* component=3 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_15 = fmul ssa_11, ssa_1
	vec1 32 ssa_16 = fmul ssa_12, ssa_1
	vec1 32 ssa_17 = fmul ssa_13, ssa_1
	vec1 32 ssa_18 = fmul ssa_14, ssa_1
	vec1 32 ssa_19 = load_const (0x00000001 /* 0.000000 */)
	vec1 32 ssa_20 = intrinsic load_uniform (ssa_19) (0, 4, 0) /* base=0 */ /* range=4 */ /* component=0 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_21 = intrinsic load_uniform (ssa_19) (0, 4, 1) /* base=0 */ /* range=4 */ /* component=1 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_22 = intrinsic load_uniform (ssa_19) (0, 4, 2) /* base=0 */ /* range=4 */ /* component=2 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_23 = intrinsic load_uniform (ssa_19) (0, 4, 3) /* base=0 */ /* range=4 */ /* component=3 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_24 = fmul ssa_20, ssa_2
	vec1 32 ssa_25 = fmul ssa_21, ssa_2
	vec1 32 ssa_26 = fmul ssa_22, ssa_2
	vec1 32 ssa_27 = fmul ssa_23, ssa_2
	vec1 32 ssa_28 = fadd ssa_15, ssa_24
	vec1 32 ssa_29 = fadd ssa_16, ssa_25
	vec1 32 ssa_30 = fadd ssa_17, ssa_26
	vec1 32 ssa_31 = fadd ssa_18, ssa_27
	vec1 32 ssa_32 = load_const (0x00000002 /* 0.000000 */)
	vec1 32 ssa_33 = intrinsic load_uniform (ssa_32) (0, 4, 0) /* base=0 */ /* range=4 */ /* component=0 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_34 = intrinsic load_uniform (ssa_32) (0, 4, 1) /* base=0 */ /* range=4 */ /* component=1 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_35 = intrinsic load_uniform (ssa_32) (0, 4, 2) /* base=0 */ /* range=4 */ /* component=2 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_36 = intrinsic load_uniform (ssa_32) (0, 4, 3) /* base=0 */ /* range=4 */ /* component=3 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_37 = fmul ssa_33, ssa_3
	vec1 32 ssa_38 = fmul ssa_34, ssa_3
	vec1 32 ssa_39 = fmul ssa_35, ssa_3
	vec1 32 ssa_40 = fmul ssa_36, ssa_3
	vec1 32 ssa_41 = fadd ssa_28, ssa_37
	vec1 32 ssa_42 = fadd ssa_29, ssa_38
	vec1 32 ssa_43 = fadd ssa_30, ssa_39
	vec1 32 ssa_44 = fadd ssa_31, ssa_40
	vec1 32 ssa_45 = load_const (0x00000003 /* 0.000000 */)
	vec1 32 ssa_46 = intrinsic load_uniform (ssa_45) (0, 4, 0) /* base=0 */ /* range=4 */ /* component=0 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_47 = intrinsic load_uniform (ssa_45) (0, 4, 1) /* base=0 */ /* range=4 */ /* component=1 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_48 = intrinsic load_uniform (ssa_45) (0, 4, 2) /* base=0 */ /* range=4 */ /* component=2 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_49 = intrinsic load_uniform (ssa_45) (0, 4, 3) /* base=0 */ /* range=4 */ /* component=3 */	/* ModelViewProjectionMatrix */
	vec1 32 ssa_50 = fadd ssa_41, ssa_46
	vec1 32 ssa_51 = fadd ssa_42, ssa_47
	vec1 32 ssa_52 = fadd ssa_43, ssa_48
	vec1 32 ssa_53 = fadd ssa_44, ssa_49
	intrinsic store_output (ssa_50, ssa_0) (0, 1, 0) /* base=0 */ /* wrmask=x */ /* component=0 */	/* gl_Position */
	intrinsic store_output (ssa_51, ssa_0) (0, 1, 1) /* base=0 */ /* wrmask=x */ /* component=1 */
	intrinsic store_output (ssa_52, ssa_0) (0, 1, 2) /* base=0 */ /* wrmask=x */ /* component=2 */
	intrinsic store_output (ssa_53, ssa_0) (0, 1, 3) /* base=0 */ /* wrmask=x */ /* component=3 */
	intrinsic store_output (ssa_8, ssa_0) (1, 1, 0) /* base=1 */ /* wrmask=x */ /* component=0 */	/* Color */
	intrinsic store_output (ssa_9, ssa_0) (1, 1, 1) /* base=1 */ /* wrmask=x */ /* component=1 */	/* Color */
	intrinsic store_output (ssa_0, ssa_0) (1, 1, 2) /* base=1 */ /* wrmask=x */ /* component=2 */	/* Color */
	intrinsic store_output (ssa_10, ssa_0) (1, 1, 3) /* base=1 */ /* wrmask=x */ /* component=3 */	/* Color */
	/* succs: block_0 */
	block block_0:
}

======== node prog seq ========
000: const 0 ssa0 pred succ 8 9 60
001: ld_att 1 ssa1 pred succ 6 15 16 17 18
002: ld_att 2 ssa2 pred succ 24 25 26 27
003: ld_att 3 ssa3 pred succ 37 38 39 40
004: const 4 ssa4 pred succ 6
005: const 5 ssa5 pred succ 8 9
006: ne 6 ssa6 pred 1 4 succ 7
007: not 7 ssa7 pred 6 succ 8 9
008: select 8 ssa8 pred 7 0 5 succ 58
009: select 9 ssa9 pred 7 5 0 succ 59
010: const 10 ssa10 pred succ 61
011: ld_uni 11 ssa11 pred succ 15
012: ld_uni 12 ssa12 pred succ 16
013: ld_uni 13 ssa13 pred succ 17
014: ld_uni 14 ssa14 pred succ 18
015: mul 15 ssa15 pred 11 1 succ 28
016: mul 16 ssa16 pred 12 1 succ 29
017: mul 17 ssa17 pred 13 1 succ 30
018: mul 18 ssa18 pred 14 1 succ 31
019: const 19 ssa19 pred succ
020: ld_uni 20 ssa20 pred succ 24
021: ld_uni 21 ssa21 pred succ 25
022: ld_uni 22 ssa22 pred succ 26
023: ld_uni 23 ssa23 pred succ 27
024: mul 24 ssa24 pred 20 2 succ 28
025: mul 25 ssa25 pred 21 2 succ 29
026: mul 26 ssa26 pred 22 2 succ 30
027: mul 27 ssa27 pred 23 2 succ 31
028: add 28 ssa28 pred 15 24 succ 41
029: add 29 ssa29 pred 16 25 succ 42
030: add 30 ssa30 pred 17 26 succ 43
031: add 31 ssa31 pred 18 27 succ 44
032: const 32 ssa32 pred succ
033: ld_uni 33 ssa33 pred succ 37
034: ld_uni 34 ssa34 pred succ 38
035: ld_uni 35 ssa35 pred succ 39
036: ld_uni 36 ssa36 pred succ 40
037: mul 37 ssa37 pred 33 3 succ 41
038: mul 38 ssa38 pred 34 3 succ 42
039: mul 39 ssa39 pred 35 3 succ 43
040: mul 40 ssa40 pred 36 3 succ 44
041: add 41 ssa41 pred 28 37 succ 50
042: add 42 ssa42 pred 29 38 succ 51
043: add 43 ssa43 pred 30 39 succ 52
044: add 44 ssa44 pred 31 40 succ 53
045: const 45 ssa45 pred succ
046: ld_uni 46 ssa46 pred succ 50
047: ld_uni 47 ssa47 pred succ 51
048: ld_uni 48 ssa48 pred succ 52
049: ld_uni 49 ssa49 pred succ 53
050: add 50 ssa50 pred 41 46 succ 54
051: add 51 ssa51 pred 42 47 succ 55
052: add 52 ssa52 pred 43 48 succ 56
053: add 53 ssa53 pred 44 49 succ 57
054: st_var 54 new pred 50 succ
055: st_var 55 new pred 51 succ
056: st_var 56 new pred 52 succ
057: st_var 57 new pred 53 succ
058: st_var 58 new pred 8 succ
059: st_var 59 new pred 9 succ
060: st_var 60 new pred 0 succ
061: st_var 61 new pred 10 succ
----------------------------
======== node prog dep ========
const 19 ssa19 input
const 32 ssa32 input
const 45 ssa45 input
st_var 54 new input
  add 50 ssa50 input
    add 41 ssa41 input
      add 28 ssa28 input
        mul 15 ssa15 input
          ld_uni 11 ssa11 input
          ld_att 1 ssa1 input
        mul 24 ssa24 input
          ld_uni 20 ssa20 input
          ld_att 2 ssa2 input
      mul 37 ssa37 input
        ld_uni 33 ssa33 input
        ld_att 3 ssa3 input
    ld_uni 46 ssa46 input
st_var 55 new input
  add 51 ssa51 input
    add 42 ssa42 input
      add 29 ssa29 input
        mul 16 ssa16 input
          ld_uni 12 ssa12 input
          ld_att 1 ssa1 input
        mul 25 ssa25 input
          ld_uni 21 ssa21 input
          ld_att 2 ssa2 input
      mul 38 ssa38 input
        ld_uni 34 ssa34 input
        ld_att 3 ssa3 input
    ld_uni 47 ssa47 input
st_var 56 new input
  add 52 ssa52 input
    add 43 ssa43 input
      add 30 ssa30 input
        mul 17 ssa17 input
          ld_uni 13 ssa13 input
          ld_att 1 ssa1 input
        mul 26 ssa26 input
          ld_uni 22 ssa22 input
          ld_att 2 ssa2 input
      mul 39 ssa39 input
        ld_uni 35 ssa35 input
        ld_att 3 ssa3 input
    ld_uni 48 ssa48 input
st_var 57 new input
  add 53 ssa53 input
    add 44 ssa44 input
      add 31 ssa31 input
        mul 18 ssa18 input
          ld_uni 14 ssa14 input
          ld_att 1 ssa1 input
        mul 27 ssa27 input
          ld_uni 23 ssa23 input
          ld_att 2 ssa2 input
      mul 40 ssa40 input
        ld_uni 36 ssa36 input
        ld_att 3 ssa3 input
    ld_uni 49 ssa49 input
st_var 58 new input
  select 8 ssa8 input
    not 7 ssa7 input
      ne 6 ssa6 input
        ld_att 1 ssa1 input
        const 4 ssa4 input
    const 0 ssa0 input
    const 5 ssa5 input
st_var 59 new input
  select 9 ssa9 input
    +not 7 ssa7 input
    const 5 ssa5 input
    const 0 ssa0 input
st_var 60 new input
  const 0 ssa0 input
st_var 61 new input
  const 10 ssa10 input
----------------------------
gpir: lower const create uniform 78 for const 0
gpir: lower const create uniform 79 for const 4
gpir: lower const create uniform 80 for const 5
gpir: lower const create uniform 81 for const 10
gpir: lower load create 82 from 78 for succ 9
gpir: lower load create 83 from 78 for succ 60
gpir: lower load create 84 from 1 for succ 15
gpir: lower load create 85 from 1 for succ 16
gpir: lower load create 86 from 1 for succ 17
gpir: lower load create 87 from 1 for succ 18
gpir: lower load create 88 from 2 for succ 25
gpir: lower load create 89 from 2 for succ 26
gpir: lower load create 90 from 2 for succ 27
gpir: lower load create 91 from 3 for succ 38
gpir: lower load create 92 from 3 for succ 39
gpir: lower load create 93 from 3 for succ 40
gpir: lower load create 94 from 80 for succ 9
gpir: pre rsched lower prog
======== node prog seq ========
000: ld_uni 78 new pred succ 8
001: ld_att 1 ssa1 pred succ 6
002: ld_att 2 ssa2 pred succ 24
003: ld_att 3 ssa3 pred succ 37
004: ld_uni 79 new pred succ 6
005: ld_uni 80 new pred succ 8
006: ne 6 ssa6 pred 1 79 succ 7
007: not 7 ssa7 pred 6 succ 8 9
008: select 8 ssa8 pred 7 78 80 succ 58
009: ld_uni 82 new pred succ 9
010: ld_uni 94 new pred succ 9
011: select 9 ssa9 pred 7 94 82 succ 59
012: ld_uni 81 new pred succ 61
013: ld_uni 11 ssa11 pred succ 15
014: ld_uni 12 ssa12 pred succ 16
015: ld_uni 13 ssa13 pred succ 17
016: ld_uni 14 ssa14 pred succ 18
017: ld_att 84 new pred succ 15
018: mul 15 ssa15 pred 11 84 succ 28
019: ld_att 85 new pred succ 16
020: mul 16 ssa16 pred 12 85 succ 29
021: ld_att 86 new pred succ 17
022: mul 17 ssa17 pred 13 86 succ 30
023: ld_att 87 new pred succ 18
024: mul 18 ssa18 pred 14 87 succ 31
025: ld_uni 20 ssa20 pred succ 24
026: ld_uni 21 ssa21 pred succ 25
027: ld_uni 22 ssa22 pred succ 26
028: ld_uni 23 ssa23 pred succ 27
029: mul 24 ssa24 pred 20 2 succ 28
030: ld_att 88 new pred succ 25
031: mul 25 ssa25 pred 21 88 succ 29
032: ld_att 89 new pred succ 26
033: mul 26 ssa26 pred 22 89 succ 30
034: ld_att 90 new pred succ 27
035: mul 27 ssa27 pred 23 90 succ 31
036: add 28 ssa28 pred 15 24 succ 41
037: add 29 ssa29 pred 16 25 succ 42
038: add 30 ssa30 pred 17 26 succ 43
039: add 31 ssa31 pred 18 27 succ 44
040: ld_uni 33 ssa33 pred succ 37
041: ld_uni 34 ssa34 pred succ 38
042: ld_uni 35 ssa35 pred succ 39
043: ld_uni 36 ssa36 pred succ 40
044: mul 37 ssa37 pred 33 3 succ 41
045: ld_att 91 new pred succ 38
046: mul 38 ssa38 pred 34 91 succ 42
047: ld_att 92 new pred succ 39
048: mul 39 ssa39 pred 35 92 succ 43
049: ld_att 93 new pred succ 40
050: mul 40 ssa40 pred 36 93 succ 44
051: add 41 ssa41 pred 28 37 succ 50
052: add 42 ssa42 pred 29 38 succ 51
053: add 43 ssa43 pred 30 39 succ 52
054: add 44 ssa44 pred 31 40 succ 53
055: ld_uni 46 ssa46 pred succ 50
056: ld_uni 47 ssa47 pred succ 51
057: ld_uni 48 ssa48 pred succ 52
058: ld_uni 49 ssa49 pred succ 53
059: add 50 ssa50 pred 41 46 succ 63
060: add 51 ssa51 pred 42 47 succ 68
061: add 52 ssa52 pred 43 48 succ 73
062: add 53 ssa53 pred 44 49 succ 62
063: mul 63 new pred 50 62 succ 65
064: ld_uni 64 new pred succ 65
065: mul 65 new pred 63 64 succ 67
066: ld_uni 66 new pred succ 67
067: add 67 new pred 65 66 succ 54
068: st_var 54 new pred 67 succ
069: mul 68 new pred 51 62 succ 70
070: ld_uni 69 new pred succ 70
071: mul 70 new pred 68 69 succ 72
072: ld_uni 71 new pred succ 72
073: add 72 new pred 70 71 succ 55
074: st_var 55 new pred 72 succ
075: mul 73 new pred 52 62 succ 75
076: ld_uni 74 new pred succ 75
077: mul 75 new pred 73 74 succ 77
078: ld_uni 76 new pred succ 77
079: add 77 new pred 75 76 succ 56
080: st_var 56 new pred 77 succ
081: rcp 62 new pred 53 succ 57 63 68 73
082: st_var 57 new pred 62 succ
083: st_var 58 new pred 8 succ
084: st_var 59 new pred 9 succ
085: ld_uni 83 new pred succ 60
086: st_var 60 new pred 83 succ
087: st_var 61 new pred 81 succ
----------------------------
gpir: after reduce scheduler
======== node prog seq ========
000: ld_uni 11 ssa11 pred succ 15
001: ld_att 84 new pred succ 15
002: mul 15 ssa15 pred 11 84 succ 28
003: ld_uni 20 ssa20 pred succ 24
004: ld_att 2 ssa2 pred succ 24
005: mul 24 ssa24 pred 20 2 succ 28
006: add 28 ssa28 pred 15 24 succ 41
007: ld_uni 33 ssa33 pred succ 37
008: ld_att 3 ssa3 pred succ 37
009: mul 37 ssa37 pred 33 3 succ 41
010: add 41 ssa41 pred 28 37 succ 50
011: ld_uni 46 ssa46 pred succ 50
012: add 50 ssa50 pred 41 46 succ 63
013: ld_uni 14 ssa14 pred succ 18
014: ld_att 87 new pred succ 18
015: mul 18 ssa18 pred 14 87 succ 31
016: ld_uni 23 ssa23 pred succ 27
017: ld_att 90 new pred succ 27
018: mul 27 ssa27 pred 23 90 succ 31
019: add 31 ssa31 pred 18 27 succ 44
020: ld_uni 36 ssa36 pred succ 40
021: ld_att 93 new pred succ 40
022: mul 40 ssa40 pred 36 93 succ 44
023: add 44 ssa44 pred 31 40 succ 53
024: ld_uni 49 ssa49 pred succ 53
025: add 53 ssa53 pred 44 49 succ 62
026: rcp 62 new pred 53 succ 57 63 68 73
027: mul 63 new pred 50 62 succ 65
028: ld_uni 64 new pred succ 65
029: mul 65 new pred 63 64 succ 67
030: ld_uni 66 new pred succ 67
031: add 67 new pred 65 66 succ 54
032: st_var 54 new pred 67 succ
033: ld_uni 12 ssa12 pred succ 16
034: ld_att 85 new pred succ 16
035: mul 16 ssa16 pred 12 85 succ 29
036: ld_uni 21 ssa21 pred succ 25
037: ld_att 88 new pred succ 25
038: mul 25 ssa25 pred 21 88 succ 29
039: add 29 ssa29 pred 16 25 succ 42
040: ld_uni 34 ssa34 pred succ 38
041: ld_att 91 new pred succ 38
042: mul 38 ssa38 pred 34 91 succ 42
043: add 42 ssa42 pred 29 38 succ 51
044: ld_uni 47 ssa47 pred succ 51
045: add 51 ssa51 pred 42 47 succ 68
046: mul 68 new pred 51 62 succ 70
047: ld_uni 69 new pred succ 70
048: mul 70 new pred 68 69 succ 72
049: ld_uni 71 new pred succ 72
050: add 72 new pred 70 71 succ 55
051: st_var 55 new pred 72 succ
052: ld_uni 13 ssa13 pred succ 17
053: ld_att 86 new pred succ 17
054: mul 17 ssa17 pred 13 86 succ 30
055: ld_uni 22 ssa22 pred succ 26
056: ld_att 89 new pred succ 26
057: mul 26 ssa26 pred 22 89 succ 30
058: add 30 ssa30 pred 17 26 succ 43
059: ld_uni 35 ssa35 pred succ 39
060: ld_att 92 new pred succ 39
061: mul 39 ssa39 pred 35 92 succ 43
062: add 43 ssa43 pred 30 39 succ 52
063: ld_uni 48 ssa48 pred succ 52
064: add 52 ssa52 pred 43 48 succ 73
065: mul 73 new pred 52 62 succ 75
066: ld_uni 74 new pred succ 75
067: mul 75 new pred 73 74 succ 77
068: ld_uni 76 new pred succ 77
069: add 77 new pred 75 76 succ 56
070: st_var 56 new pred 77 succ
071: st_var 57 new pred 62 succ
072: ld_att 1 ssa1 pred succ 6
073: ld_uni 79 new pred succ 6
074: ne 6 ssa6 pred 1 79 succ 7
075: not 7 ssa7 pred 6 succ 8 9
076: ld_uni 78 new pred succ 8
077: ld_uni 80 new pred succ 8
078: select 8 ssa8 pred 7 78 80 succ 58
079: st_var 58 new pred 8 succ
080: ld_uni 94 new pred succ 9
081: ld_uni 82 new pred succ 9
082: select 9 ssa9 pred 7 94 82 succ 59
083: st_var 59 new pred 9 succ
084: ld_uni 83 new pred succ 60
085: st_var 60 new pred 83 succ
086: ld_uni 81 new pred succ 61
087: st_var 61 new pred 81 succ
----------------------------
gpir: post rsched lower prog
======== node prog seq ========
000: ld_uni 11 ssa11 pred succ 15
001: ld_att 84 new pred succ 15
002: mul 15 ssa15 pred 11 84 succ 28
003: ld_uni 20 ssa20 pred succ 24
004: ld_att 2 ssa2 pred succ 24
005: mul 24 ssa24 pred 20 2 succ 28
006: add 28 ssa28 pred 15 24 succ 41
007: ld_uni 33 ssa33 pred succ 37
008: ld_att 3 ssa3 pred succ 37
009: mul 37 ssa37 pred 33 3 succ 41
010: add 41 ssa41 pred 28 37 succ 50
011: ld_uni 46 ssa46 pred succ 50
012: add 50 ssa50 pred 41 46 succ 63
013: ld_uni 14 ssa14 pred succ 18
014: ld_att 87 new pred succ 18
015: mul 18 ssa18 pred 14 87 succ 31
016: ld_uni 23 ssa23 pred succ 27
017: ld_att 90 new pred succ 27
018: mul 27 ssa27 pred 23 90 succ 31
019: add 31 ssa31 pred 18 27 succ 44
020: ld_uni 36 ssa36 pred succ 40
021: ld_att 93 new pred succ 40
022: mul 40 ssa40 pred 36 93 succ 44
023: add 44 ssa44 pred 31 40 succ 53
024: ld_uni 49 ssa49 pred succ 53
025: add 53 ssa53 pred 44 49 succ 62 95 96
026: complex2 95 new pred 53 succ 62
027: rcp_impl 96 new pred 53 succ 62
028: complex1 62 new pred 53 96 95 succ 100
029: dummy_f 101 new pred succ 100
030: dummy_m 100 new pred 62 101 succ 57 63 68 73
031: mul 63 new pred 50 100 succ 65
032: ld_uni 64 new pred succ 65
033: mul 65 new pred 63 64 succ 67
034: ld_uni 66 new pred succ 67
035: add 67 new pred 65 66 succ 54
036: st_var 54 new pred 67 succ
037: ld_uni 12 ssa12 pred succ 16
038: ld_att 85 new pred succ 16
039: mul 16 ssa16 pred 12 85 succ 29
040: ld_uni 21 ssa21 pred succ 25
041: ld_att 88 new pred succ 25
042: mul 25 ssa25 pred 21 88 succ 29
043: add 29 ssa29 pred 16 25 succ 42
044: ld_uni 34 ssa34 pred succ 38
045: ld_att 91 new pred succ 38
046: mul 38 ssa38 pred 34 91 succ 42
047: add 42 ssa42 pred 29 38 succ 51
048: ld_uni 47 ssa47 pred succ 51
049: add 51 ssa51 pred 42 47 succ 68
050: mul 68 new pred 51 100 succ 70
051: ld_uni 69 new pred succ 70
052: mul 70 new pred 68 69 succ 72
053: ld_uni 71 new pred succ 72
054: add 72 new pred 70 71 succ 55
055: st_var 55 new pred 72 succ
056: ld_uni 13 ssa13 pred succ 17
057: ld_att 86 new pred succ 17
058: mul 17 ssa17 pred 13 86 succ 30
059: ld_uni 22 ssa22 pred succ 26
060: ld_att 89 new pred succ 26
061: mul 26 ssa26 pred 22 89 succ 30
062: add 30 ssa30 pred 17 26 succ 43
063: ld_uni 35 ssa35 pred succ 39
064: ld_att 92 new pred succ 39
065: mul 39 ssa39 pred 35 92 succ 43
066: add 43 ssa43 pred 30 39 succ 52
067: ld_uni 48 ssa48 pred succ 52
068: add 52 ssa52 pred 43 48 succ 73
069: mul 73 new pred 52 100 succ 75
070: ld_uni 74 new pred succ 75
071: mul 75 new pred 73 74 succ 77
072: ld_uni 76 new pred succ 77
073: add 77 new pred 75 76 succ 56
074: st_var 56 new pred 77 succ
075: st_var 57 new pred 100 succ
076: ld_att 1 ssa1 pred succ 97 98
077: ld_uni 79 new pred succ 97 98
078: lt 97 new pred 1 79 succ 6
079: lt 98 new pred 1 79 succ 6
080: max 6 ssa6 pred 97 98 succ 102
081: dummy_f 103 new pred succ 102
082: dummy_m 102 new pred 6 103 succ 7
083: const 99 new pred succ 7
084: add 7 ssa7 pred 102 99 succ 8 9
085: ld_uni 78 new pred succ 8
086: ld_uni 80 new pred succ 8
087: select 8 ssa8 pred 7 78 80 succ 104
088: dummy_f 105 new pred succ 104
089: dummy_m 104 new pred 8 105 succ 58
090: st_var 58 new pred 104 succ
091: ld_uni 94 new pred succ 9
092: ld_uni 82 new pred succ 9
093: select 9 ssa9 pred 7 94 82 succ 106
094: dummy_f 107 new pred succ 106
095: dummy_m 106 new pred 9 107 succ 59
096: st_var 59 new pred 106 succ
097: ld_uni 83 new pred succ 60
098: st_var 60 new pred 83 succ
099: ld_uni 81 new pred succ 61
100: st_var 61 new pred 81 succ
----------------------------
======== value regalloc ========
000: 11/0 ld_uni
001: 84/1 ld_att
002: 15/2 mul  11/0 84/1
003: 20/3 ld_uni
004: 2/4 ld_att
005: 24/5 mul  20/3 2/4
006: 28/6 add  15/2 24/5
007: 33/7 ld_uni
008: 3/8 ld_att
009: 37/9 mul  33/7 3/8
010: 41/10 add  28/6 37/9
011: 46/0 ld_uni
012: 50/1 add  41/10 46/0
013: 14/2 ld_uni
014: 87/3 ld_att
015: 18/4 mul  14/2 87/3
016: 23/5 ld_uni
017: 90/6 ld_att
018: 27/7 mul  23/5 90/6
019: 31/8 add  18/4 27/7
020: 36/9 ld_uni
021: 93/10 ld_att
022: 40/0 mul  36/9 93/10
023: 44/2 add  31/8 40/0
024: 49/3 ld_uni
025: 53/3 add  44/2 49/3
026: 95/4 complex2  53/3
027: 96/5 rcp_impl  53/3
028: 62/6 complex1  53/3 96/5 95/4
029: 101/7 dummy_f
030: 100/8 dummy_m  62/6 101/7
031: 63/9 mul  50/1 100/8
032: 64/10 ld_uni
033: 65/0 mul  63/9 64/10
034: 66/1 ld_uni
035: 67/2 add  65/0 66/1
036: 54/-1 st_var  67/2
037: 12/3 ld_uni
038: 85/4 ld_att
039: 16/5 mul  12/3 85/4
040: 21/6 ld_uni
041: 88/7 ld_att
042: 25/9 mul  21/6 88/7
043: 29/9 add  16/5 25/9
044: 34/10 ld_uni
045: 91/0 ld_att
046: 38/1 mul  34/10 91/0
047: 42/2 add  29/9 38/1
048: 47/3 ld_uni
049: 51/4 add  42/2 47/3
050: 68/5 mul  51/4 100/8
051: 69/6 ld_uni
052: 70/7 mul  68/5 69/6
053: 71/9 ld_uni
054: 72/9 add  70/7 71/9
055: 55/-1 st_var  72/9
056: 13/10 ld_uni
057: 86/0 ld_att
058: 17/1 mul  13/10 86/0
059: 22/2 ld_uni
060: 89/3 ld_att
061: 26/4 mul  22/2 89/3
062: 30/5 add  17/1 26/4
063: 35/6 ld_uni
064: 92/7 ld_att
065: 39/9 mul  35/6 92/7
066: 43/9 add  30/5 39/9
067: 48/10 ld_uni
068: 52/0 add  43/9 48/10
069: 73/1 mul  52/0 100/8
070: 74/2 ld_uni
071: 75/3 mul  73/1 74/2
072: 76/4 ld_uni
073: 77/5 add  75/3 76/4
074: 56/-1 st_var  77/5
075: 57/-1 st_var  100/8
076: 1/6 ld_att
077: 79/7 ld_uni
078: 97/8 lt  1/6 79/7
079: 98/9 lt  1/6 79/7
080: 6/10 max  97/8 98/9
081: 103/0 dummy_f
082: 102/1 dummy_m  6/10 103/0
083: 99/2 const
084: 7/3 add  102/1 99/2
085: 78/4 ld_uni
086: 80/5 ld_uni
087: 8/6 select  7/3 78/4 80/5
088: 105/7 dummy_f
089: 104/8 dummy_m  8/6 105/7
090: 58/-1 st_var  104/8
091: 94/9 ld_uni
092: 82/10 ld_uni
093: 9/0 select  7/3 94/9 82/10
094: 107/1 dummy_f
095: 106/2 dummy_m  9/0 107/1
096: 59/-1 st_var  106/2
097: 83/3 ld_uni
098: 60/-1 st_var  83/3
099: 81/4 ld_uni
100: 61/-1 st_var  81/4
----------------------------
======== physical regalloc ========
----------------------------
instr 0 for ready list: 60/r 61/r 58/r 59/r
gpir: remain fully ready node 60
gpir: fully ready max node 83
gpir: create move 108 for 83
gpir: fully ready max node 108
gpir: fully ready max node 83
gpir: remain fully ready node 61
gpir: fully ready max node 81
gpir: create move 109 for 81
gpir: fully ready max node 109
gpir: fully ready max node 81
gpir: remain fully ready node 58
gpir: fully ready max node 8
gpir: instr 0 spill move 109 from slot 1 to 3
gpir: fully ready max node 80
gpir: fully ready max node 78
gpir: same load 83 in instr 0 for node 78
gpir: remain fully ready node 59
gpir: fully ready max node 9
gpir: create move 110 for 9
gpir: fully ready max node 110
gpir: remain fully ready node 9
gpir: remain fully ready node 56
post schedule instr 0/8 1/8 2/108 3/109 4/110 15/83 17/80 18/81 19/58 20/59 21/60 22/61
instr 1 for ready list: 9/r 7/p 56/r
gpir: remain fully ready node 9
gpir: fully ready max node 94
gpir: fully ready max node 82
gpir: remain fully ready node 7
gpir: remain fully ready node 56
gpir: partially ready max node 77
gpir: create move 111 for 77
gpir: fully ready max node 111
gpir: remain fully ready node 7
post schedule instr 0/9 1/9 2/111 15/82 17/94 21/56
instr 2 for ready list: 7/r 77/p
gpir: fully ready max node 7
gpir: remain fully ready node 77
gpir: fully ready max node 76
gpir: remain fully ready node 99
gpir: remain fully ready node 6
post schedule instr 2/7 3/77 17/76
instr 3 for ready list: 99/r 6/r 75/p
gpir: remain fully ready node 99
gpir: remain fully ready node 6
gpir: remain fully ready node 75
gpir: fully ready max node 74
gpir: remain fully ready node 6
post schedule instr 1/75 2/99 17/74
instr 4 for ready list: 6/r 73/p
gpir: fully ready max node 6
gpir: remain fully ready node 97
gpir: remain fully ready node 98
post schedule instr 2/6
instr 5 for ready list: 97/r 73/p 98/r
gpir: partially ready max node 73
gpir: create move 112 for 73
gpir: fully ready max node 112
gpir: remain fully ready node 97
gpir: instr 5 spill move 112 from slot 2 to 0
gpir: partially ready max node 79
gpir: create move 113 for 79
gpir: remain fully ready node 98
gpir: remain fully ready node 73
gpir: remain fully ready node 1
gpir: remain fully ready node 73
gpir: remain fully ready node 113
gpir: remain fully ready node 57
gpir: partially ready max node 62
gpir: create move 114 for 62
gpir: partially ready max node 114
gpir: remain fully ready node 73
gpir: remain fully ready node 113
post schedule instr 0/112 1/114 2/97 3/98 7/1 22/57
instr 6 for ready list: 73/r 113/r 62/p
gpir: remain fully ready node 73
gpir: remain fully ready node 52
gpir: remain fully ready node 113
gpir: fully ready max node 79
gpir: remain fully ready node 52
post schedule instr 1/73 2/113 16/79
instr 7 for ready list: 52/r 62/p
gpir: partially ready max node 62
gpir: create move 115 for 62
gpir: partially ready max node 115
gpir: remain fully ready node 52
gpir: instr 7 spill move 115 from slot 2 to 0
gpir: fully ready max node 48
gpir: remain fully ready node 43
post schedule instr 0/115 2/52 17/48
instr 8 for ready list: 43/r 62/p
gpir: remain fully ready node 43
gpir: remain fully ready node 39
gpir: remain fully ready node 30
post schedule instr 2/43
instr 9 for ready list: 39/r 30/r 62/p
gpir: partially ready max node 62
gpir: create move 116 for 62
gpir: partially ready max node 116
gpir: remain fully ready node 39
gpir: fully ready max node 35
gpir: remain fully ready node 92
gpir: remain fully ready node 55
gpir: fully ready max node 72
gpir: instr 9 spill move 116 from slot 2 to 0
gpir: fully ready max node 71
gpir: create move 117 for 71
gpir: remain fully ready node 30
gpir: remain fully ready node 70
gpir: remain fully ready node 26
gpir: remain fully ready node 117
gpir: remain fully ready node 17
post schedule instr 0/116 1/39 2/72 3/30 9/92 17/35 20/55
instr 10 for ready list: 70/r 26/r 117/r 17/r 62/p
gpir: >5 ready node 70
gpir: fully ready max node 69
gpir: remain fully ready node 26
gpir: fully ready max node 22
gpir: create move 118 for 22
gpir: remain fully ready node 68
gpir: remain fully ready node 89
gpir: remain fully ready node 68
gpir: remain fully ready node 118
gpir: remain fully ready node 117
gpir: fully ready max node 71
gpir: create move 119 for 71
gpir: remain fully ready node 68
gpir: remain fully ready node 118
gpir: remain fully ready node 17
gpir: remain fully ready node 119
post schedule instr 0/26 1/70 2/117 8/89 16/69
instr 11 for ready list: 68/r 118/r 17/r 119/r 62/p
gpir: fully ready max node 17
gpir: fully ready max node 13
gpir: partially ready max node 62
gpir: create move 120 for 62
gpir: partially ready max node 120
gpir: remain fully ready node 68
gpir: remain fully ready node 118
gpir: fully ready max node 22
gpir: create move 121 for 22
gpir: remain fully ready node 121
gpir: remain fully ready node 119
gpir: fully ready max node 71
gpir: create move 122 for 71
gpir: remain fully ready node 121
gpir: remain fully ready node 122
gpir: remain fully ready node 86
gpir: remain fully ready node 121
gpir: remain fully ready node 122
post schedule instr 0/68 1/17 2/120 3/118 4/119 7/86 17/13
instr 12 for ready list: 121/r 51/p 122/r 62/p
gpir: remain fully ready node 121
gpir: fully ready max node 22
gpir: remain fully ready node 51
gpir: instr 12 spill move 121 from slot 2 to 0
gpir: fully ready max node 47
gpir: create move 123 for 47
gpir: remain fully ready node 122
gpir: fully ready max node 71
gpir: create move 124 for 71
gpir: remain fully ready node 124
gpir: remain fully ready node 123
post schedule instr 0/121 1/122 2/51 17/22
instr 13 for ready list: 124/r 42/p 123/r 62/p
gpir: partially ready max node 62
gpir: create move 125 for 62
gpir: partially ready max node 125
gpir: remain fully ready node 124
gpir: fully ready max node 71
gpir: remain fully ready node 42
gpir: instr 13 spill move 125 from slot 2 to 0
gpir: remain fully ready node 38
gpir: remain fully ready node 29
gpir: remain fully ready node 54
gpir: partially ready max node 67
gpir: create move 126 for 67
gpir: fully ready max node 126
gpir: remain fully ready node 38
gpir: remain fully ready node 29
gpir: remain fully ready node 123
gpir: fully ready max node 47
gpir: create move 127 for 47
gpir: remain fully ready node 38
gpir: remain fully ready node 29
gpir: remain fully ready node 127
post schedule instr 0/125 1/124 2/42 3/126 4/123 16/71 19/54
instr 14 for ready list: 38/r 29/r 67/p 127/r 62/p
gpir: >5 ready node 38
gpir: fully ready max node 34
gpir: remain fully ready node 29
gpir: remain fully ready node 91
gpir: remain fully ready node 67
gpir: fully ready max node 66
gpir: create move 128 for 66
gpir: remain fully ready node 127
gpir: fully ready max node 47
gpir: create move 129 for 47
gpir: remain fully ready node 25
gpir: remain fully ready node 129
gpir: remain fully ready node 128
post schedule instr 0/127 1/38 2/29 3/67 9/91 16/34
instr 15 for ready list: 25/r 129/r 16/p 65/p 128/r 62/p
gpir: partially ready max node 62
gpir: create move 130 for 62
gpir: partially ready max node 130
gpir: remain fully ready node 25
gpir: fully ready max node 21
gpir: remain fully ready node 129
gpir: fully ready max node 47
gpir: create move 131 for 47
gpir: remain fully ready node 131
gpir: remain fully ready node 65
gpir: fully ready max node 64
gpir: create move 132 for 64
gpir: remain fully ready node 131
gpir: remain fully ready node 128
gpir: fully ready max node 66
gpir: create move 133 for 66
gpir: remain fully ready node 131
gpir: remain fully ready node 133
gpir: remain fully ready node 88
gpir: remain fully ready node 131
gpir: remain fully ready node 133
gpir: remain fully ready node 132
post schedule instr 0/65 1/25 2/130 3/129 4/128 8/88 16/21
instr 16 for ready list: 131/r 16/p 133/r 63/p 62/p 132/r
gpir: partially ready max node 16
gpir: create move 134 for 16
gpir: fully ready max node 134
gpir: >5 ready node 131
gpir: fully ready max node 47
gpir: remain fully ready node 133
gpir: fully ready max node 66
gpir: create move 135 for 66
gpir: remain fully ready node 16
gpir: remain fully ready node 135
gpir: remain fully ready node 132
gpir: fully ready max node 64
gpir: create move 136 for 64
gpir: remain fully ready node 16
gpir: remain fully ready node 135
gpir: remain fully ready node 136
post schedule instr 0/132 1/131 2/134 3/133 16/47
instr 17 for ready list: 16/r 135/r 63/p 62/p 136/r
gpir: partially ready max node 63
gpir: create move 137 for 63
gpir: fully ready max node 137
gpir: partially ready max node 62
gpir: create move 138 for 62
gpir: partially ready max node 138
gpir: remain fully ready node 16
gpir: instr 17 spill move 138 from slot 1 to 0
gpir: fully ready max node 12
gpir: remain fully ready node 135
gpir: fully ready max node 66
gpir: create move 139 for 66
gpir: remain fully ready node 139
gpir: remain fully ready node 85
gpir: remain fully ready node 139
gpir: remain fully ready node 136
gpir: fully ready max node 64
gpir: create move 140 for 64
gpir: remain fully ready node 139
gpir: remain fully ready node 140
post schedule instr 0/138 1/16 2/137 3/135 4/136 7/85 16/12
instr 18 for ready list: 139/r 63/p 62/p 140/r
gpir: remain fully ready node 139
gpir: fully ready max node 66
gpir: remain fully ready node 63
gpir: remain fully ready node 62
gpir: remain fully ready node 140
gpir: fully ready max node 64
gpir: create move 141 for 64
gpir: remain fully ready node 62
gpir: remain fully ready node 141
post schedule instr 1/63 2/139 3/140 15/66
instr 19 for ready list: 62/r 141/r 50/p
gpir: fully ready max node 62
gpir: create move 142 for 62
gpir: fully ready max node 142
gpir: remain fully ready node 62
gpir: remain fully ready node 141
gpir: fully ready max node 64
gpir: remain fully ready node 62
post schedule instr 1/141 2/142 15/64
instr 20 for ready list: 62/r 50/p
gpir: partially ready max node 50
gpir: create move 143 for 50
gpir: fully ready max node 143
gpir: remain fully ready node 62
post schedule instr 2/143
instr 21 for ready list: 62/r 50/p
gpir: fully ready max node 62
gpir: remain fully ready node 96
gpir: remain fully ready node 95
post schedule instr 0/62 1/62
instr 22 for ready list: 96/r 95/r 53/p 50/p
gpir: fully ready max node 96
gpir: partially ready max node 50
gpir: create move 144 for 50
gpir: fully ready max node 144
gpir: remain fully ready node 95
gpir: remain fully ready node 53
post schedule instr 0/95 2/144 5/96
instr 23 for ready list: 53/r 50/p
gpir: fully ready max node 53
gpir: fully ready max node 49
gpir: remain fully ready node 44
post schedule instr 2/53 18/49
instr 24 for ready list: 44/r 50/p
gpir: partially ready max node 50
gpir: create move 145 for 50
gpir: fully ready max node 145
gpir: remain fully ready node 44
gpir: instr 24 spill move 145 from slot 2 to 0
gpir: remain fully ready node 31
gpir: remain fully ready node 40
post schedule instr 0/145 2/44
instr 25 for ready list: 31/r 40/r 50/p
gpir: remain fully ready node 31
gpir: remain fully ready node 40
gpir: fully ready max node 36
gpir: remain fully ready node 27
gpir: remain fully ready node 93
gpir: remain fully ready node 27
gpir: remain fully ready node 50
gpir: fully ready max node 46
gpir: create move 146 for 46
gpir: remain fully ready node 27
gpir: remain fully ready node 18
gpir: remain fully ready node 146
post schedule instr 1/40 2/31 3/50 9/93 18/36
instr 26 for ready list: 27/r 18/r 41/p 146/r
gpir: remain fully ready node 27
gpir: fully ready max node 23
gpir: remain fully ready node 18
gpir: fully ready max node 14
gpir: create move 147 for 14
gpir: remain fully ready node 90
gpir: remain fully ready node 41
gpir: remain fully ready node 147
gpir: remain fully ready node 146
gpir: fully ready max node 46
gpir: create move 148 for 46
gpir: remain fully ready node 147
gpir: remain fully ready node 87
gpir: remain fully ready node 147
gpir: remain fully ready node 148
gpir: remain fully ready node 37
post schedule instr 0/18 1/27 2/41 3/146 7/87 8/90 18/23
instr 27 for ready list: 147/r 28/p 148/r 37/r
gpir: remain fully ready node 147
gpir: fully ready max node 14
gpir: remain fully ready node 28
gpir: instr 27 spill move 147 from slot 2 to 0
gpir: remain fully ready node 148
gpir: fully ready max node 46
gpir: create move 149 for 46
gpir: remain fully ready node 149
gpir: remain fully ready node 37
gpir: instr 27 spill move 148 from slot 1 to 3
gpir: fully ready max node 33
gpir: create move 150 for 33
gpir: remain fully ready node 149
gpir: remain fully ready node 24
gpir: remain fully ready node 3
gpir: remain fully ready node 149
gpir: remain fully ready node 24
gpir: remain fully ready node 150
post schedule instr 0/147 1/37 2/28 3/148 9/3 18/14
instr 28 for ready list: 149/r 15/p 24/r 150/r
gpir: remain fully ready node 149
gpir: fully ready max node 46
gpir: remain fully ready node 15
gpir: fully ready max node 11
gpir: create move 151 for 11
gpir: remain fully ready node 24
gpir: fully ready max node 20
gpir: create move 152 for 20
gpir: remain fully ready node 150
gpir: fully ready max node 33
gpir: create move 153 for 33
gpir: remain fully ready node 84
gpir: remain fully ready node 151
gpir: remain fully ready node 2
gpir: remain fully ready node 151
gpir: remain fully ready node 152
gpir: remain fully ready node 153
post schedule instr 0/24 1/15 2/149 3/150 7/84 8/2 15/46
instr 29 for ready list: 151/r 152/r 153/r
gpir: remain fully ready node 151
gpir: fully ready max node 11
gpir: remain fully ready node 152
gpir: fully ready max node 20
gpir: create move 154 for 20
gpir: remain fully ready node 153
gpir: fully ready max node 33
gpir: create move 155 for 33
gpir: remain fully ready node 154
gpir: remain fully ready node 155
post schedule instr 1/152 2/151 3/153 15/11
instr 30 for ready list: 154/r 155/r
gpir: remain fully ready node 154
gpir: fully ready max node 20
gpir: remain fully ready node 155
gpir: fully ready max node 33
gpir: create move 156 for 33
gpir: remain fully ready node 156
post schedule instr 1/155 2/154 15/20
instr 31 for ready list: 156/r
gpir: remain fully ready node 156
gpir: fully ready max node 33
post schedule instr 2/156 15/33
====== gpir scheduler statistic ======
---- how many nodes are scheduled ----
       mov:49           mul:18        select:2       complex1:1
  complex2:1            add:16            lt:2            max:1
  rcp_impl:1         ld_uni:29        ld_att:13        st_var:8
     const:1

total: 142
---- how many nodes are created ----
       mov:49

total: 49
------------------------------------
========prog instr========
     mul0 mul1 add0 add1 pass cmpl bnch load0           load1           load2           store
000: null null 156  null null null null |||             |||             33|||           |||
001: null 155  154  null null null null |||             |||             20|||           |||
002: null 152  151  153  null null null |||             |||             11|||           |||
003: 24   15   149  150  null null null 84|2||          |||             46|||           |||
004: 147  37   28   148  null null null ||3|            |||             |||14           |||
005: 18   27   41   146  null null null 87|90||         |||             |||23           |||
006: null 40   31   50   null null null ||93|           |||             |||36           |||
007: 145  null 44   null null null null |||             |||             |||             |||
008: null null 53   null null null null |||             |||             |||49           |||
009: 95   null 144  null null 96   null |||             |||             |||             |||
010: 62   62   null null null null null |||             |||             |||             |||
011: null null 143  null null null null |||             |||             |||             |||
012: null 141  142  null null null null |||             |||             64|||           |||
013: null 63   139  140  null null null |||             |||             66|||           |||
014: 138  16   137  135  136  null null 85|||           |||             |12||           |||
015: 132  131  134  133  null null null |||             |||             |47||           |||
016: 65   25   130  129  128  null null |88||           |||             |21||           |||
017: 127  38   29   67   null null null ||91|           |||             |34||           |||
018: 125  124  42   126  123  null null |||             |||             |71||           54|||
019: 121  122  51   null null null null |||             |||             ||22|           |||
020: 68   17   120  118  119  null null 86|||           |||             ||13|           |||
021: 26   70   117  null null null null |89||           |||             |69||           |||
022: 116  39   72   30   null null null ||92|           |||             ||35|           |55||
023: null null 43   null null null null |||             |||             |||             |||
024: 115  null 52   null null null null |||             |||             ||48|           |||
025: null 73   113  null null null null |||             |||             |79||           |||
026: 112  114  97   98   null null null 1|||            |||             |||             |||57
027: null null 6    null null null null |||             |||             |||             |||
028: null 75   99   null null null null |||             |||             ||74|           |||
029: null null 7    77   null null null |||             |||             ||76|           |||
030: 9    9    111  null null null null |||             |||             82||94|         ||56|
031: 8    8    108  109  110  null null |||             |||             83||80|81       58|59|60|61
-----------------------
==========================
000: b30ad6b5 03808ab5 0007ff80 000ad500
001: b30b42b5 03804ab5 0007ff80 000ad500
002: b30b42b5 03802ad3 0007ff80 000ad500
003: b3004033 4380ead1 0007ff80 000ad500
004: 94c146cf 438022d0 0007ff80 000ad500
005: 9c00bc12 438062d1 0007ff80 000ad500
006: 9c813eb5 43808230 0007ff80 000ad500
007: 9c0ad6d1 038002b5 0007ff80 000ad500
008: 7c0ad6b5 0380c2b5 0007ff80 000ad500
009: b68ad610 03800ab5 0147ff80 000ac130
010: ad4c5a56 038002b5 0007ff80 000ad510
011: b60ad6b5 03800ab5 0007ff80 000ad500
012: b68b32b5 03810ab5 0007ff80 000ad500
013: b30862b5 03816ad3 0007ff80 000ad500
014: b4c036d8 43802ad0 0007ff80 0008d500
015: b4cb36d4 0380ead1 0007ff80 000ad500
016: b680b658 43806ad3 0007ff80 0008d500
017: 9e0136d1 43808292 0007ff80 000ad500
018: 9c0b36d8 038162d1 4007fc80 00095500
019: a40b4ece 038042b5 0007ff80 000ad500
020: b6803b50 43802ad2 0007ff80 0009d500
021: b506c831 43810ab5 0007ff80 000ad500
022: 84c13ad8 4380825b 4007e380 000ad500
023: 9c4ad6b5 038002b5 0007ff80 000ad500
024: 740ad6da 0380c2b5 0007ff80 000ad500
025: b34942b5 03818ab5 0007ff80 000ad500
026: 800b6ad3 43800010 002bff80 000ad508
027: 8c0ad6b5 038002b5 003fff80 000ad500
028: 00076ab5 038102b5 0007ff80 000ad500
029: c40ad6b5 038149d3 0007ff80 000ad500
030: b44aba0c 03818ab5 00071f80 000ad548
031: b30ab30e 0381aacf c4011100 00095548
 FPS: 59 FrameTime: 16.949 ms
=======================================================
                                  glmark2 Score: 59
=======================================================