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a guest Jul 21st, 2019 110 Never
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  1. module video_ram (
  2.   input wire vram_clk,          // Input: Clock for vram read latch.
  3.   input wire [14:0] vram_addr,  // Input: Address for vram port.
  4.   output wire [3:0] vram_out     // Output: Vram port.
  5. );
  6.   //memory declaration.
  7.   reg [7:0] ram[0:9600];
  8.   initial $readmemh("possum.hex", ram);
  9.  
  10.   reg [7:0] vram_out_i;
  11.  
  12.   //Reading from the RAM in 4-bit chunks
  13.   always @(posedge vram_clk)
  14.     vram_out_i <= ram[vram_addr[14:1]];
  15.  
  16.   always @(posedge vram_clk)
  17.     lsb <= vram_addr[0];
  18.  
  19.   assign vram_out = lsb ? vram_out_i[7:4] : vram_out_i[3:0];
  20.  
  21. endmodule
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