ENTITY uc IS
    GENERIC (delay: TIME := 10 ns);
    PORT(clock, reset: IN BIT;
        start: IN BIT;
        q1,q0,r,cnt: IN BIT;
        --stop c7 c6 c5 c4 c3 c2 c1 c0
        controls: OUT BIT_VECTOR(7 downto 0));
END ENTITY;
ARCHITECTURE funct OF uc IS
TYPE stari IS (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10);
SIGNAL afisare_stare: stari;

BEGIN

PROCESS (clock)
VARIABLE stare: stari:=s0;
VARIABLE concat: BIT_VECTOR(2 downto 0);
BEGIN
    IF clock='1' AND clock'EVENT THEN
        CASE stare IS
            WHEN s0 =>
                controls<="00000000";
                if start = '1' then
                    stare:=s1;
                else stare:=s0;
                end if;
            WHEN s1 =>
                controls<="00000001";
                stare:=s2;
            WHEN s2 =>
                controls<="00000010";
                stare:=s3;
            WHEN s3 =>
                controls<="00000000";
                concat(0):=r;
                concat(1):=q0;
                concat(2):=q1;
                --test conditions
                if concat = "001" or concat = "010" then
                    stare:=s4;
                elsif concat = "101" or concat = "110" then
                    stare:=s5;
                else
                    stare:=s6;
                end if;
            WHEN s4 =>
                controls<="00000100";
                stare:=s6;
            WHEN s5 =>
                controls<="00001100";
                stare:=s6;
            WHEN s6 =>
                controls<="00010000";
                stare:=s7;
            WHEN s7 =>
                if cnt = '1' then
                    stare:=s8;
                else
                    stare:=s3;
                end if;
            WHEN s8 =>
                controls<="00100000";
                stare:=s9;
            WHEN s9 =>
                controls<="01000000";
                stare:=s10;
            WHEN s10 =>
                controls<="10000000";
                --return to start
                stare:=s0;
        END CASE;
     END IF;
END PROCESS;
END ARCHITECTURE;