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porta_and

Jul 25th, 2019
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VHDL 0.37 KB | None | 0 0
  1. --PORTA AND 3 ENTRADAS
  2. --ENTRADAS: entrada0, entrada1, entrada2 (in bit)
  3. --SAIDAS:   saida (out bit)
  4. --AUTORES: MARCOS MEIRA, JOÃO VITOR
  5. --DATA: 30/01/2018
  6.  
  7. entity porta_and is
  8.     port (entrada0, entrada1, entrada2: in bit;
  9.           saida: out bit);
  10. end porta_and;
  11.  
  12. architecture arquitetura of porta_and is
  13. begin
  14.     saida <= entrada0 and entrada1 and entrada2;
  15. end arquitetura;
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