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May 26th, 2017
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VHDL 0.59 KB | None | 0 0
  1.     process(clock, reset)
  2.     begin
  3.         if rising_edge(clock) then
  4.             fifo_count <= fifo_count + 1;
  5.             fifo_wren <= '0';
  6.             if (fifo_count > 10 and fifo_count < 30) or (fifo_count > 35) then
  7.                 if fifo_almost_full = '0' then
  8.                     fifo_wren <= '1';
  9.                     fifo_din <= std_logic_vector(fifo_count);
  10.                 end if;
  11.             end if;
  12.  
  13.             fifo_rdack <= '0';
  14.             if fifo_valid = '1' then
  15.                 foo <= fifo_dout;
  16.                 fifo_rdack <= '1';
  17.             end if;
  18.         end if;
  19.        
  20.         if reset = '1' then
  21.             fifo_count <= (others => '0');
  22.             fifo_wren <= '0';
  23.             fifo_rdack <= '0';
  24.             fifo_valid_reg <= '0';
  25.         end if;
  26.     end process;
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