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vuk123456789 Apr 28th, 2018 59 Never
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  1. -- Copyright (C) 1991-2013 Altera Corporation
  2. -- Your use of Altera Corporation's design tools, logic functions
  3. -- and other software and tools, and its AMPP partner logic
  4. -- functions, and any output files from any of the foregoing
  5. -- (including device programming or simulation files), and any
  6. -- associated documentation or information are expressly subject
  7. -- to the terms and conditions of the Altera Program License
  8. -- Subscription Agreement, Altera MegaCore Function License
  9. -- Agreement, or other applicable license agreement, including,
  10. -- without limitation, that your use is for the sole purpose of
  11. -- programming logic devices manufactured by Altera and sold by
  12. -- Altera or its authorized distributors.  Please refer to the
  13. -- applicable agreement for further details.
  14.  
  15. -- ***************************************************************************
  16. -- This file contains a Vhdl test bench template that is freely editable to  
  17. -- suit user's needs .Comments are provided in each section to help the user  
  18. -- fill out necessary details.                                                
  19. -- ***************************************************************************
  20. -- Generated on "04/28/2018 18:28:30"
  21.                                                            
  22. -- Vhdl Test Bench template for design  :  state_slat
  23. --
  24. -- Simulation tool : ModelSim-Altera (VHDL)
  25. --
  26.  
  27. LIBRARY ieee;                                              
  28. USE ieee.std_logic_1164.all;                                
  29.  
  30. ENTITY state_slat_vhd_tst IS
  31. END state_slat_vhd_tst;
  32. ARCHITECTURE state_slat_arch OF state_slat_vhd_tst IS
  33. -- constants                                  
  34. constant clk_period: time := 20 ns;          
  35. -- signals                                                  
  36. SIGNAL clk : STD_LOGIC;
  37. SIGNAL izbaci_slatko : STD_LOGIC;
  38. SIGNAL reset : STD_LOGIC := '1';
  39. SIGNAL ubaci_5 : STD_LOGIC := '0';
  40. SIGNAL ubaci_10 : STD_LOGIC := '0';
  41. COMPONENT state_slat
  42.     PORT (
  43.     clk : IN STD_LOGIC;
  44.     izbaci_slatko : OUT STD_LOGIC;
  45.     reset : IN STD_LOGIC;
  46.     ubaci_5 : IN STD_LOGIC;
  47.     ubaci_10 : IN STD_LOGIC
  48.     );
  49. END COMPONENT;
  50. BEGIN
  51.     i1 : state_slat
  52.     PORT MAP (
  53. -- list connections between master ports and signals
  54.     clk => clk,
  55.     izbaci_slatko => izbaci_slatko,
  56.     reset => reset,
  57.     ubaci_5 => ubaci_5,
  58.     ubaci_10 => ubaci_10
  59.     );
  60.  
  61.  
  62. clk_process : PROCESS                                              
  63. -- variable declarations                                    
  64. BEGIN                                                        
  65.     clk <= '0';
  66.     wait for clk_period/2;
  67.     clk <= '1';
  68.     wait for clk_period/2;                                                      
  69. END PROCESS clk_process;        
  70.  
  71.                                          
  72. always : PROCESS                                              
  73. -- optional sensitivity list                                  
  74. -- (        )                                                
  75. -- variable declarations                                      
  76. BEGIN                                                        
  77.         -- code executes for every event on sensitivity list  
  78.     reset <= '1';
  79.     wait for 3*clk_period;
  80.     reset <= '0';
  81.    
  82.     ubaci_5 <= '1';
  83.     wait for clk_period;
  84.     ubaci_5 <= '0';
  85.  
  86.     wait for 3*clk_period;
  87.  
  88.     ubaci_5 <= '1';
  89.     wait for clk_period;
  90.     ubaci_5 <= '0';
  91.  
  92.  
  93.  
  94. WAIT;                                                        
  95. END PROCESS always;                                          
  96. END state_slat_arch;
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