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-- Company:
-- Engineer:
--
-- Create Date:    16:54:29 12/11/2011
-- Design Name:
-- Module Name:    data_ram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_ram is
--  GENERIC (pDATA_WIDTH : integer :=8;
--              pADRESS_WIDTH : integer:=4;
--              pNO_OF_WORDS: integer:=16);
--
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iA : in  STD_LOGIC_VECTOR (4 downto 0);--padress
           iD : in  STD_LOGIC_VECTOR (15 downto 0);--pdata
           iWE : in  STD_LOGIC;
           oQ : out  STD_LOGIC_VECTOR (15 downto 0));
end data_ram;

architecture Behavioral of data_ram is
type tRAM IS ARRAY (15 downto 0) of std_LOGIC_VECTOR (7 downto 0);
SIGNAL sRAM:tRAM;


begin
    process (iCLK) begin
        if (RISING_EDGE(iCLK)) then
            if (inRST='0') then
                sRAM(0)<="00000000";
                sRAM( 1)<="00000000";
                sRAM( 2)<="00000000";
                sRAM( 3)<="00000000";
                sRAM( 4)<="00000000";
                sRAM( 5)<="00000000";
                sRAM( 6)<="00000000";
                sRAM( 7)<="00000000";
                sRAM( 8)<="00000000";
                sRAM( 9)<="00000000";
                sRAM( 10)<="00000000";
                sRAM( 11)<="00000000";
                sRAM( 12)<="00000000";
                sRAM( 13)<="00000000";
                sRAM( 14)<="00000000";
                sRAM( 15)<="00000000";
            elsif (iWE= '1') then
                sRAM( Conv_INTEGER(iA))<=iD;
            end if;
        end if;
    end process;

    process (iCLK) begin
        if (RISING_EDGE(iCLK)) then
            if (inRST='0') then
                oQ<=(others => 'Z');
            elsif (iWE= '0') then
                oQ<=sRAM( Conv_INTEGER(iA));
            else
                oQ<=(others => 'Z');
            end if;
        end if;
    end process;

end Behavioral;