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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- use IEEE.numeric_std.all;
- entity ramem is
- port
- (
- RW : in std_logic;
- RE : in std_logic;
- clk : in std_logic;
- data : in std_logic_vector(15 downto 0);
- addr : in std_logic_vector(3 downto 0);
- q : out std_logic_vector(15 downto 0)
- );
- end ramem;
- architecture rtl of ramem is
- -- Build a 2-D array type for the RAM
- type RAM is array(15 downto 0) of std_logic_vector(15 downto 0);
- signal memory : RAM:= (others => X"0000");
- signal lastButtonState1 : std_logic := '0';
- signal lastButtonState2 : std_logic := '0';
- begin
- process(clk)
- begin
- if(rising_edge(clk)) then
- if(RE='1' and lastButtonState1='0') then
- memory <= ("0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000",
- "0000000000000000");
- elsif(RW='1' and lastButtonState2='0') then
- memory(to_integer(unsigned(addr))) <= data;
- end if;
- lastButtonState1 <= RE;
- lastButtonState2 <= RW;
- q <= memory(to_integer(unsigned(addr)));
- end if;
- end process;
- end rtl;
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