----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    13:59:21 02/01/2019
-- Design Name:
-- Module Name:    half_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity half_adder is
    Port ( Ain : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           sout : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end half_adder;

architecture Behavioral of half_adder is

begin
    sout <= Ain xor Bin;
    cout <= Ain and Bin;

end Behavioral;