PSDS zadatak 2.1 (brojac)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity i_kolo is
    Port ( x1 : in STD_LOGIC;
           x2 : in STD_LOGIC;
           y : out STD_LOGIC);
end i_kolo;

architecture Behavioral of i_kolo is

begin
    process(x1, x2) is
    begin

        y <= x1 and x2;

    end process;
end Behavioral;


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dec_counter is
    Port ( en : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk : in STD_LOGIC;
           q : out STD_LOGIC_VECTOR (3 downto 0);
           pulse : out STD_LOGIC);
end dec_counter;

architecture Behavioral of dec_counter is
    signal count_s: std_logic_vector(3 downto 0) := (others => '0');
begin
    cnt: process (clk) is
    begin
        if(clk'event and clk = '1') then
            if(reset = '1') then
                count_s <= (others => '0');
            else
                if(en = '1') then
                    if(count_s < conv_std_logic_vector(9, 4)) then
                        count_s <= count_s + 1;
                    else
                        count_s <= (others => '0');
                    end if;
                end if;
             end if;
        end if;
    end process;

    q <= count_s;
    pulse <= '1' when  count_s =  "1001" and en = '1' else
    '0';

end Behavioral;


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity top_level is
    Port ( en : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk : in STD_LOGIC;
           q0 : out STD_LOGIC_VECTOR(3 downto 0);
           q1 : out STD_LOGIC_VECTOR(3 downto 0);
           q2 : out STD_LOGIC_VECTOR(3 downto 0));
end top_level;

architecture Behavioral of top_level is
    signal pom1, pom2: std_logic;
    signal jed, des, stot: std_logic_vector(3 downto 0);
    signal izlaz_i_kola: std_logic;
begin
    jedinice: entity work.dec_counter(Behavioral)
              port map(
                    clk => clk,
                    reset => reset,
                    en => en,
                    pulse => pom1,
                    q => jed);

    desetice: entity work.dec_counter(Behavioral)
              port map(
                    clk => clk,
                    reset => reset,
                    en => pom1,
                    pulse => pom2,
                    q => des);

    i_kolo: entity work.i_kolo(Behavioral)
             port map(
                    x1 => pom1,
                    x2 => pom2,
                    y => izlaz_i_kola);

    stotine: entity work.dec_counter(Behavioral)
             port map(
                    clk => clk,
                    reset => reset,
                    en => izlaz_i_kola,
                    pulse => open,
                    q => stot);

        q0 <= jed;
        q1 <= des;
        q2 <= stot;

end Behavioral;


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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity test_benc is
--  Port ( );
end test_benc;

architecture Behavioral of test_benc is
    signal en_s, clk_s, reset_s:std_logic;
    signal  q_s0, q_s1, q_s2: std_logic_vector(3 downto 0);
begin
    brojac: entity work.top_level (Behavioral)
        port map(
            en => en_s,
            clk => clk_s,
            reset => reset_s,
            q0 => q_s0,
            q1 => q_s1,
            q2 => q_s2);

    signali: process
    begin
        en_s <= '1';
        reset_s <= '0';
        clk_s <= '0', '1' after 100 ns ;
            wait for 200 ns;
    end process;

end Behavioral;