adc - dma - timer init

    ADC1->CR2 |= ADC_CR2_EXTSEL; // SWSTART
    ADC1->CR2 |= ADC_CR2_EXTTRIG;
    ADC1->SMPR2 |= ADC_SAMPLETIME_239CYCLES_5;
    ADC1->CR2 |= ADC_CR2_ADON;
    ADC1->CR2 |= ADC_CR2_DMA;

    HAL_Delay(2);
    ADC1->CR2 |= ADC_CR2_CAL;
    HAL_Delay(2);

    HAL_NVIC_DisableIRQ(DMA1_Channel1_IRQn);
    DMA1_Channel1->CCR |= DMA_CCR_TCIE;
    DMA1_Channel1->CCR |= DMA_CCR_MSIZE_0;
    DMA1_Channel1->CCR |= DMA_CCR_PSIZE_0;
    DMA1_Channel1->CCR |= DMA_CCR_CIRC;
    DMA1_Channel1->CNDTR = 10;
    DMA1_Channel1->CPAR = (uint32_t)&(ADC1->DR);
    DMA1_Channel1->CMAR = (uint32_t)&(TIM2->CCR1);

    DMA1_Channel1->CCR |= DMA_CCR_EN;
    ADC1->CR2 |= ADC_CR2_SWSTART;

    TIM2->CCMR2 |= TIM_CCMR1_OC1CE; // OC1PE: Output compare 1 preload enable
    TIM2->CCMR2 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_0); // PWM mode 2 - In upcounting, channel 1 is inactive
    TIM2->CCER  |= TIM_CCER_CC1E; // Capture/Compare 1 output to pin enable
    //TIM2->PSC    = 0xFFFF; // Prescaler value
    TIM2->ARR    = 0xFFF; // ARR is the value to be loaded in the actual auto-reload register.
    //TIM2->CCR4   = 0x40; // Capture/Compare 1 value
    TIM2->CR1   |= TIM_CR1_CEN; // Counter enable