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  1. #if !defined(__cplusplus)
  2. #include <stdbool.h>
  3. #endif
  4. #include <stddef.h>
  5. #include <stdint.h>
  6.  
  7. #define CONFIG_TX_DESCR_NUM   16
  8. #define CONFIG_RX_DESCR_NUM   16
  9. #define CONFIG_ETH_BUFSIZE    2048
  10.  
  11. #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
  12. #define DMA_PBL               (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
  13. #define TX_TOTAL_BUFSIZE      (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  14. #define RX_TOTAL_BUFSIZE      (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  15. #define MAC_MAX_FRAME_SZ      1600
  16. #define DESC_RXCTRL_RXCHAIN   (1 << 24)
  17. #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
  18. #define DESC_RXSTS_OWNBYDMA   (1 << 31)
  19. #define STOREFORWARD          (1 << 21)
  20. #define FLUSHTXFIFO           (1 << 20)
  21. #define FIXEDBURST            (1 << 16)
  22. #define PRIORXTX_41           (3 << 14)
  23. #define RXSTART               (1 << 1)
  24. #define RXENABLE              (1 << 2)
  25. #define FULLDUPLEX            (1 << 11)
  26. #define LINKUP                (1 << 8)
  27.  
  28. // The UART registers base address.
  29. #define UART0_BASE 0x01C28000
  30. // The offsets for reach register for the UART.
  31. #define UART0_RBR (UART0_BASE + 0x00)
  32. #define UART0_THR (UART0_BASE + 0x00)
  33. #define UART0_IER (UART0_BASE + 0x04)
  34. #define UART0_FCR (UART0_BASE + 0x08)
  35. #define UART0_LSR (UART0_BASE + 0x14)
  36. #define UART0_USR (UART0_BASE + 0x7C)
  37.  
  38. // The GMAC registers base address.
  39. #define GMAC_BASE         0x01C50000
  40. // The offsets for reach register for the GMAC.
  41. #define GMAC_CONTROL      (GMAC_BASE + 0x00)
  42. #define GMAC_FRAME_FILTER (GMAC_BASE + 0x04)
  43. #define GMAC_GMII_ADDR    (GMAC_BASE + 0x10)
  44. #define GDMA_RCV_LIST     (GMAC_BASE + 0x100C)
  45. #define GDMA_BUS_MODE     (GMAC_BASE + 0x1000)
  46. #define GDMA_OPERATION    (GMAC_BASE + 0x1018)
  47.  
  48. // The DRAM base address.
  49. #define DRAM_BASE 0x40000000
  50.  
  51. struct dmamacdescr {
  52.   volatile uint32_t txrx_status;
  53.   volatile uint32_t dmamac_cntl;
  54.   volatile void *dmamac_addr;
  55.   struct dmamacdescr *dmamac_next;
  56. };
  57.  
  58. // Set up some pointers to locations in DRAM for GMAC DMA
  59. volatile char *txbuf = (void*)(DRAM_BASE + 0x0);
  60. volatile char *rxbuf = (void*)(DRAM_BASE + 0x8000);
  61. struct dmamacdescr *tx_mac_descrtable = (void*)(DRAM_BASE + 0x10000);
  62. struct dmamacdescr *rx_mac_descrtable = (void*)(DRAM_BASE + 0x10100);
  63. uint32_t rx_idx = 0;
  64. uint32_t tx_idx = 0;
  65.  
  66. static inline void mmio_write(uint32_t reg, uint32_t data)
  67. {
  68.     *(volatile uint32_t *)reg = data;
  69. }
  70.  
  71. static inline uint32_t mmio_read(uint32_t reg)
  72. {
  73.     return *(volatile uint32_t *)reg;
  74. }
  75.  
  76. /* Loop <delay> times in a way that the compiler won't optimize away. */
  77. static inline void delay(int32_t count)
  78. {
  79.     asm volatile("__delay_%=: subs %[count], %[count], #1; bne __delay_%=\n"
  80.          : : [count]"r"(count) : "cc");
  81. }
  82.  
  83. size_t strlen(const char* str)
  84. {
  85.     size_t ret = 0;
  86.     while ( str[ret] != 0 )
  87.         ret++;
  88.     return ret;
  89. }
  90.  
  91. void uart_init()
  92. {
  93.     // Disable UART interrupts.
  94.     mmio_write(UART0_IER, 0x00000000);
  95.  
  96.     // Configure UART (enable FIFO)
  97.     mmio_write(UART0_FCR, 0x00000001);
  98.  
  99. }
  100.  
  101. unsigned char uart_tx_ready()
  102. {
  103.   return mmio_read(UART0_USR) & (2);
  104. }
  105.  
  106. unsigned char uart_rx_ready()
  107. {
  108.   return mmio_read(UART0_LSR) & (1);
  109. }
  110.  
  111. void uart_putc(unsigned char byte)
  112. {
  113.     // Wait for UART transmit FIFO to be not full.
  114.   while ( ! uart_tx_ready() );
  115.     mmio_write(UART0_THR, byte);
  116. }
  117.  
  118. unsigned char uart_getc()
  119. {
  120.     // Wait for UART to have recieved something.
  121.     while ( ! uart_rx_ready() );
  122.     return mmio_read(UART0_RBR);
  123. }
  124.  
  125. void uart_write(const unsigned char* buffer, size_t size)
  126. {
  127.     for ( size_t i = 0; i < size; i++ )
  128.         uart_putc(buffer[i]);
  129. }
  130.  
  131. void uart_puts(const char* str)
  132. {
  133.     uart_write((const unsigned char*) str, strlen(str));
  134. }
  135.  
  136. void uart_puts_uint32(uint32_t number)
  137. {
  138.   unsigned char chars[] = "0123456789ABCDEF";
  139.   uart_putc(chars[(number >> 28) & 0xF]);
  140.   uart_putc(chars[(number >> 24) & 0xF]);
  141.   uart_putc(chars[(number >> 20) & 0xF]);
  142.   uart_putc(chars[(number >> 16) & 0xF]);
  143.   uart_putc(chars[(number >> 12) & 0xF]);
  144.   uart_putc(chars[(number >> 8) & 0xF]);
  145.   uart_putc(chars[(number >> 4) & 0xF]);
  146.   uart_putc(chars[(number >> 0) & 0xF]);
  147. }
  148.  
  149. volatile void *memset(volatile void *s, int c, size_t n)
  150. {
  151.     volatile unsigned char* p=s;
  152.     while(n--)
  153.         *p++ = (unsigned char)c;
  154.     return s;
  155. }
  156.  
  157. void gmac_init()
  158. {
  159.   // Reset GMAC DMA
  160.   uart_puts("Resetting GMAC DMA... ");
  161.   mmio_write(GDMA_BUS_MODE, (mmio_read(GDMA_BUS_MODE) | 1));
  162.   while (mmio_read(GDMA_BUS_MODE) & 1) {}
  163.   uart_puts("[DONE]\r\n");
  164.  
  165.   // Zero-fill buffers
  166.   memset(rxbuf, 0, 1024*32);
  167.   memset(txbuf, 0, 1024*32);
  168.  
  169.   // Set up RX buffer descriptors
  170.   uart_puts("Configuring RX buffers... ");
  171.   uint32_t idx;
  172.   struct dmamacdescr *desc_p;
  173.   for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  174.     desc_p = rx_mac_descrtable + idx;
  175.  
  176.     desc_p->dmamac_addr = &rxbuf[idx * CONFIG_ETH_BUFSIZE];
  177.     desc_p->dmamac_next = rx_mac_descrtable + idx + 1;
  178.  
  179.     desc_p->dmamac_cntl =
  180.       (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
  181.               DESC_RXCTRL_RXCHAIN;
  182.  
  183.     desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  184.   }
  185.   desc_p->dmamac_next = rx_mac_descrtable;
  186.  
  187.   // Configure GMAC DMA with RX buffer descriptors
  188.   mmio_write(GDMA_RCV_LIST, (uint32_t)rx_mac_descrtable);
  189.   uart_puts("[DONE]\r\n");
  190.  
  191.   mmio_write(GDMA_BUS_MODE, FIXEDBURST | PRIORXTX_41 | DMA_PBL);
  192.   mmio_write(GDMA_OPERATION, mmio_read(GDMA_OPERATION) | FLUSHTXFIFO | STOREFORWARD);
  193.   mmio_write(GDMA_OPERATION, mmio_read(GDMA_OPERATION) | RXSTART);
  194.   mmio_write(GMAC_CONTROL, mmio_read(GMAC_CONTROL) | RXENABLE);
  195.   mmio_write(GMAC_CONTROL, mmio_read(GMAC_CONTROL) | FULLDUPLEX | LINKUP);
  196.   //priv->tx_currdescnum = 0;
  197.  
  198.   //int n;
  199.   //for(n=0;n<=0x1054; n=n+4)
  200.   //{
  201.   //  uart_puts_uint32(n);
  202.   //  uart_putc(' ');
  203.   //  uart_puts_uint32(mmio_read(GMAC_BASE + n));
  204.   //  uart_putc('\r');
  205.   //  uart_putc('\n');
  206.   //}
  207. }
  208.  
  209. #if defined(__cplusplus)
  210. extern "C" /* Use C linkage for kernel_main. */
  211. #endif
  212. void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags)
  213. {
  214.   (void) r0;
  215.   (void) r1;
  216.   (void) atags;
  217.  
  218.     uart_init();
  219.     uart_puts("Hello, kernel World!\r\n");
  220.   gmac_init();
  221.   uart_puts_uint32(mmio_read(GMAC_CONTROL));
  222.   uart_puts("\r\n");
  223.   struct dmamacdescr *desc_p;
  224.  
  225.     while ( true )
  226.   {
  227.     desc_p = rx_mac_descrtable + rx_idx;
  228.     while(desc_p->txrx_status & DESC_RXSTS_OWNBYDMA);
  229.     desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  230.     rx_idx++;
  231.     if(rx_idx > 15) rx_idx = 0;
  232.     uart_puts("Frame received!\r\n");
  233.   }
  234. }
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