4bitripplecarryadder.vhd

--Design
library ieee;
use ieee.std_logic_1164.all;

entity fourbitadder is
    port(x,y: in std_logic_vector(3 downto 0);
           s: out std_logic_vector(4 downto 0));
end fourbitadder;


architecture boole of fourbitadder is

    --De carry out, der bliver sendt mellem hver adder
    signal m: std_logic_vector(4 downto 0);

component fulladder is
    port(a, b, c: in std_logic;
        s: out std_logic;
        t: out std_logic);
end component;

--Interface fra fulladder til fulladder
begin
    m(0)<='0';
        bcount1: fulladder port map (a=>x(0), b=>y(0), c=>m(0), t=>m(1), s=>s(0)
    );
        bcount2: fulladder port map (a=>x(1), b=>y(1), c=>m(1), t=>m(2), s=>s(1)
    );
    bcount3: fulladder port map (a=>x(2), b=>y(2), c=>m(2), t=>m(3), s=>s(2)
    );
    bcount4: fulladder port map (a=>x(3), b=>y(3), c=>m(3), t=>s(4), s=>s(3)
    );


end boole;