testarevhdl

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-- Company:
-- Engineer:
--
-- Create Date: 05/11/2018 03:24:04 PM
-- Design Name:
-- Module Name: testare - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testare is
Port(
        Clk : in STD_LOGIC;
        Rst : in STD_LOGIC;
        Read : in STD_LOGIC;
        Sel : in STD_LOGIC;
        MISO : in STD_LOGIC;
        MOSI : out STD_LOGIC;
        SkLK : out STD_LOGIC;
        SS : out STD_LOGIC;
        An : out STD_LOGIC_VECTOR(7 downto 0);
        Seg : out STD_LOGIC_VECTOR(7 downto 0)
    );

end testare;

architecture Behavioral of testare is
signal ReadEn : STD_LOGIC := '0';
signal Data : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal Data1 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal Data2 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');

begin

accelerometer_map : entity WORK.adxl port map(
    Clk => Clk,
    Rst => Rst,
    Read => ReadEn,
    MISO => MISO,
    MOSI => MOSI,
    SKLK => SKLK,
    SS => SS,
    Data1 => Data1,
    Data2 => Data2
);

Data <= Data1 when Sel = '0' else Data2;

debouncer_map : entity WORK.debounce1 port map(
    Clk => Clk,
    Rst => Rst,
    D_in => Read,
    Q_out => ReadEn
);
ssd_map : entity WORK.displ7seg port map(
    Clk => Clk,
    Rst => Rst,
    Data => Data,
    An => An,
    Seg => Seg
);

end Behavioral;