----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    08:44:54 10/18/2017
-- Design Name:
-- Module Name:    ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end ALU;

architecture Behavioral of ALU is

begin
process(f0,f1)
begin
if (f0='0' and f1='0') then
  Y<=A+B;
  elsif  (f0='1' and f1='0') then
  Y<=A-B;
  end if;
end process;
end Behavioral;


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:03:22 10/18/2017
-- Design Name:
-- Module Name:    ALU2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU2 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end ALU2;

architecture Behavioral of ALU2 is

begin
Y<= A and B;
end Behavioral;


- Company:
-- Engineer:
--
-- Create Date:    09:05:37 10/18/2017
-- Design Name:
-- Module Name:    ALU3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU3 is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end ALU3;

architecture Behavioral of ALU3 is

begin
Y<= A and B;
end Behavioral;


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:09:02 10/18/2017
-- Design Name:
-- Module Name:    MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX is
    Port ( i0 : in  STD_LOGIC_VECTOR (4 downto 0);
           i1 : in  STD_LOGIC_VECTOR (4 downto 0);
           i2 : in  STD_LOGIC_VECTOR (4 downto 0);
           i3 : in  STD_LOGIC_VECTOR (4 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end MUX;

architecture Behavioral of MUX is

begin
Y<= i0 when (f1='0' and f0='0') else
        i1 when (f1='0' and f0='1') else
        i2 when (f1='1' and f0='0') else
        i3;

end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:20:29 10/18/2017
-- Design Name:
-- Module Name:    ALU_D - str_arch
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_D is

end ALU_D;
port (Af : in  STD_LOGIC_VECTOR (3 downto 0);
           Bf : in  STD_LOGIC_VECTOR (3 downto 0);
           f0f : in  STD_LOGIC;
           f1f : in  STD_LOGIC;
           Yf : out  STD_LOGIC_VECTOR (4 downto 0));
architecture str_arch of ALU_D is
component ALU
port (A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
              end component;
component ALU2
 Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;

component ALU3
Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;
component MUX
Port ( i0 : in  STD_LOGIC_VECTOR (4 downto 0);
           i1 : in  STD_LOGIC_VECTOR (4 downto 0);
           i2 : in  STD_LOGIC_VECTOR (4 downto 0);
           i3 : in  STD_LOGIC_VECTOR (4 downto 0);
           f0 : in  STD_LOGIC;
           f1 : in  STD_LOGIC;
           Y : out  STD_LOGIC_VECTOR (4 downto 0));
end component;

signal p1,p2,p3 : 4 downto 0;

begin
unit1: ALU port map ()

end str_arch;