library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_gates is
port(a,b: in std_logic;
and_out,or_out,xor_out: out std_logic);
end;

architecture test of my_gates is
function my_xor(s1: std_logic;s2: std_logic) return std_logic is
    begin
        return (s1 xor s2);
    end my_xor;


procedure my_and_or(signal s1:in std_logic;signal s2:in std_logic;signal and_out, or_out: out std_logic) is
    begin
        or_out<=(s1 or s2);
        and_out<=(s1 and s2);
    end my_and_or;

begin
xor_out<=my_xor(a,b);
my_and_or(a,b,and_out,or_out);
end;