rom1

----------------------------------------------------------------------------------
-- Logicko projektovanje racunarskih sistema 1
-- 2011/2012
-- Lab 7
--
-- Instruction ROM
--
-- author: Branislav Nikolic, e13592
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity instr_rom is
    Port ( iA : in  STD_LOGIC_VECTOR (4 downto 0);
           oQ : out  STD_LOGIC_VECTOR (14 downto 0));
end instr_rom;

architecture Behavioral of instr_rom is

    -- ALU instructions --
    constant cMOV : std_logic_vector(5 downto 0) := "000000";
    constant cADD : std_logic_vector(5 downto 0) := "000001";
    constant cSUB : std_logic_vector(5 downto 0) := "000010";
    constant cAND : std_logic_vector(5 downto 0) := "000011";
    constant cOR : std_logic_vector(5 downto 0) := "000100";
    constant cNOT : std_logic_vector(5 downto 0) := "000101";
    constant cINC : std_logic_vector(5 downto 0) := "000110";
    constant cDEC : std_logic_vector(5 downto 0) := "000111";
    constant cSHL : std_logic_vector(5 downto 0) := "001000";
    constant cSHR : std_logic_vector(5 downto 0) := "001001";
    constant cASHL : std_logic_vector(5 downto 0) := "001010";
    constant cASHR : std_logic_vector(5 downto 0) := "001011";
    constant cJMP:  std_logic_vector(5 downto 0) :="010000";
    constant cJMPZ:  std_logic_vector(5 downto 0) :="010001";
    constant cJMPS:  std_logic_vector(5 downto 0) :="010010";
    constant cJMC:  std_logic_vector(5 downto 0) :="010011";
    constant cJMPNZ:  std_logic_vector(5 downto 0) :="010101";
    constant cJMPNS:  std_logic_vector(5 downto 0) :="010110";
    constant cJMNC:  std_logic_vector(5 downto 0) :="010111";

    -- Other instructions --
    constant cLD : std_logic_vector(5 downto 0) := "100000";
    constant cST : std_logic_vector(5 downto 0) := "110000";

    -- Registers --
    constant cR0 : std_logic_vector(2 downto 0) := "000";
    constant cR1 : std_logic_vector(2 downto 0) := "001";
    constant cR2 : std_logic_vector(2 downto 0) := "010";
    constant cR3 : std_logic_vector(2 downto 0) := "011";
    constant cR4 : std_logic_vector(2 downto 0) := "100";
    constant cR5 : std_logic_vector(2 downto 0) := "101";
    constant cR6 : std_logic_vector(2 downto 0) := "110";
    constant cR7 : std_logic_vector(2 downto 0) := "111";
    constant cRX : std_logic_vector(2 downto 0) := "---"; -- reg field not used

begin
 process(iA)begin
    case (iA)is

--COUNTER_DEFINE:
    when "00000" =>oQ<= cLD &cR0 &cRX &cR0;
    when "00001" =>oQ <= cINC   &cR0  &cR0  & cRX; --R0=1
    when "00010" =>oQ<= cASHL   &cR0  &cR0  & cRX; --R0=2
    when "00011" =>oQ<= cASHL  &cR0  &cR0  & cRX; --COUNTER R0=4
--PARAMETER_DEFINE:

    when "00100" =>oQ<= cLD &cR1 &cRX &cR1;
    when "00101" =>oQ<= cLD &cR3 &cRX &cR3;
    when "00110" =>oQ <= cINC   &cR1  &cR1  & cRX; --R1=1
    when "00111" =>oQ <= cINC   &cR1  &cR1  & cRX; --R1=2, DODELA VREDNOSTI ZA FALSE PROVERE2

    when "01000" =>oQ<= cASHL  &cR3  &cR1  & cRX; --R3=4
    when "01001" =>oQ<= cASHL  &cR3  &cR3  & cRX; --R3=8, DRUGA PROVERA

--BLOCS:
    when "01010" =>oQ<=cDEC  &cR0 & cR0 & cRX; --DECREMENT COUNTER
    when "01011" => oQ<= cJMPZ &"000000100";
    when "01100" => oQ<= cLD &cR2 &cRX &cR2;
    when "01101" => oQ<= cLD &cR7 &cRX &cR7;
    when "01110" => oQ<= cINC &cR2 &cR2 &cRX;
    when "01111" => oQ<= cINC &cR2 &cR2 &cRX; --R2=2
    when "10000" => oQ<= cASHL  &cR7  &cR2  &cRX; --R7=4
--  when "01110" => oQ<= cASHL  &cR7  &cR2  &cRX; --R7=8
        when "10001" => oQ<= cSUB &cR6 &cR7 &cR3;
    when "10010" =>oQ<= cJMPZ &"000010011";--TRUE

--INTRUCTION_FALSE
    when "10011" => oQ<= cMOV &cR4 &cR1 &cRX;
    when "10100" =>oQ<= cJMP &"000000100";

--INSTRUCTION TRUE
    when "10101"=>oQ<= cOR &cR5 &cR2 &cR7;
    when "10110"=>oQ<= cJMP &"000000100";

    when others => oQ<= (others => '0');

    end case;
end process;


end Behavioral;