entity vjezba is
port(
clk_in, switch: STD_LOGIC;
led: out STD_LOGIC_VECTOR(2 downto 0)
);
end vjezba;

architecture Behavioral of vjezba is
signal clk_out: std_logic;

begin
label1:entity work.generic_divider generic map(12_500_000) port map(clk_in, clk_out);
process(clk_out, switch)
variable temp:std_logic_vector(2 downto 0) :="000";
begin
if(clk_out'EVENT AND clk_out = '1' and switch = '1') then
temp :=temp+1;
end if;
led<=temp;
end process;
end Behavioral;