library ieee;
use ieee.std_logic_1164.all;

entity sum_1_bit is
    port
    (
    a,b,cin : in std_logic;
    s, cout: out std_logic
    );
end entity;

architecture sum of sum_1_bit is
begin
    cout <= (a and b) or (a and cin) or (b and cin);
    s <= a xor b xor cin;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity sum_n_biti is
    generic (n : INTEGER range 0 to 10 := 5);
    port
    (
    a,b : in std_logic_vector (n-1 downto 0);
    cin : in std_logic;
    cout : out std_logic;
    s : out std_logic_vector (n-1 downto 0)
    );
end entity;

architecture summ of sum_n_biti is
component sum_1_bit is
    port
    (
    a,b,cin : in std_logic;
    s, cout: out std_logic
    );
end component;
signal temp : std_logic_vector (n-1 downto 0);
begin
    et1: for i in 0 to n - 1 generate
        et2: if i = 0 generate
            et3: sum_1_bit port map(a(i), b(i), cin, s(i), temp(i));
        end generate;
        et4: if i > 0 and i < n generate
            et5: sum_1_bit port map(a(i), b(i), temp(i-1), s(i), temp(i));
        end generate;
        et6: if i = n generate
            et7: sum_1_bit port map(a(i), b(i), temp(i-1), s(i), cout);
        end generate;
    end generate;
end architecture;