Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.NUMERIC_STD.ALL;
- use IEEE.NUMERIC_BIT.ALL;
- entity pic is
- port (
- CLK_50MHz : in STD_LOGIC;
- PIX_X : in STD_LOGIC_VECTOR(9 downto 0);
- PIX_Y : in STD_LOGIC_VECTOR(8 downto 0);
- RGB : out STD_LOGIC_VECTOR(2 downto 0)
- );
- end pic;
- architecture Behavioral of pic is
- signal cnt : integer range 0 to 50000000 := 0;
- signal cnt2 : integer range 0 to 50000000 := 0;
- --type RGB_ARR is array (0 to 5) of std_logic_vector(2 downto 0);
- signal P_Y,P_X : integer range 0 to 800 := 0;
- --signal ARR : RGB_ARR := ( "001", "010", "100", "011", "110", "101");
- signal ARR : std_logic_vector(17 downto 0) := ( "001010100011110101");
- signal ULX : integer := 31;
- signal ULY : integer := 215;
- begin
- P_Y <= To_Integer(Unsigned(PIX_Y));
- P_X <= To_Integer(Unsigned(PIX_X));
- -- 50000000 clocks per sec
- counter: process(CLK_50MHz)
- begin
- if rising_edge(CLK_50MHz) then
- if cnt2 < 1666667 then
- cnt2 <= cnt2 + 1;
- else
- cnt2 <= 0;
- if ULX < 600 then
- ULX <= ULX + 1;
- else
- ULX <= 0;
- end if;
- end if;
- if cnt < 50000000 then
- cnt <= cnt + 1;
- else
- cnt <= 0;
- ARR <= ARR(14 downto 0) & ARR(17 downto 15);
- end if;
- end if;
- end process counter;
- vertical: process(P_Y,P_X)
- begin
- if (P_Y < 240) then
- if (P_X < 213) then
- RGB <= ARR(2 downto 0);
- elsif (P_X < 426) then
- RGB <= ARR(5 downto 3);
- else
- RGB <= ARR(8 downto 6);
- end if;
- else
- if (P_X < 213) then
- RGB <= ARR(11 downto 9);
- elsif (P_X < 426) then
- RGB <= ARR(14 downto 12);
- else
- RGB <= ARR(17 downto 15);
- end if;
- end if;
- if (P_Y > ULY and P_Y < ULY+50) then
- if (P_X > ULX and P_X < ULX + 50) then
- RGB <= "000";
- end if;
- end if;
- end process vertical;
- end Behavioral;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement