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lpc_emac vs sun4i_emac

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  1. http://svn.openrobotino.org/firmware/EA09/trunk/src/LPC23_EMAC.c
  2. http://svn.openrobotino.org/firmware/EA09/trunk/src/LPC23_EMAC.h <--- bit defs, very similar to sun4i_emac
  3. http://www.keil.com/dd/docs/arm/philips/lpc23xx.h                   <-registers like below
  4. _______________________________________________________________________________________________________________
  5. /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
  6. #define MAC_BASE_ADDR       0xFFE00000 /* AHB Peripheral # 0 */
  7. #define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
  8. #define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
  9. #define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
  10. #define MAC_IPGR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
  11. #define MAC_CLRT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
  12. #define MAC_MAXF            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
  13. #define MAC_SUPP            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
  14. #define MAC_TEST            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
  15. #define MAC_MCFG            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
  16. #define MAC_MCMD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
  17. #define MAC_MADR            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
  18. #define MAC_MWTD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
  19. #define MAC_MRDD            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
  20. #define MAC_MIND            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
  21.  
  22. #define MAC_SA0             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
  23. #define MAC_SA1             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
  24. #define MAC_SA2             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
  25.  
  26. #define MAC_COMMAND         (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
  27. #define MAC_STATUS          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
  28. #define MAC_RXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
  29. #define MAC_RXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
  30. #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
  31. #define MAC_RXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
  32. #define MAC_RXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
  33. #define MAC_TXDESCRIPTOR    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
  34. #define MAC_TXSTATUS        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
  35. #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
  36. #define MAC_TXPRODUCEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
  37. #define MAC_TXCONSUMEINDEX  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
  38.  
  39. #define MAC_TSV0            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
  40. #define MAC_TSV1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
  41. #define MAC_RSV             (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
  42.  
  43. #define MAC_FLOWCONTROLCNT  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
  44. #define MAC_FLOWCONTROLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
  45.  
  46. #define MAC_RXFILTERCTRL    (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
  47. #define MAC_RXFILTERWOLSTS  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
  48. #define MAC_RXFILTERWOLCLR  (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
  49.  
  50. #define MAC_HASHFILTERL     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
  51. #define MAC_HASHFILTERH     (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
  52.  
  53. #define MAC_INTSTATUS       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
  54. #define MAC_INTENABLE       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
  55. #define MAC_INTCLEAR        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
  56. #define MAC_INTSET          (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
  57.  
  58. #define MAC_POWERDOWN       (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
  59. #define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
  60. __________________________________________________________________________________________________________________
  61. from linux/drivers/net/ethernet/allwinner/sun4i-emac.h
  62.  
  63. #define EMAC_CTL_REG        (0x00)
  64. #define EMAC_TX_MODE_REG    (0x04)
  65.  
  66. #define EMAC_TX_FLOW_REG    (0x08)
  67. #define EMAC_TX_CTL0_REG    (0x0c)
  68. #define EMAC_TX_CTL1_REG    (0x10)
  69. #define EMAC_TX_INS_REG     (0x14)
  70. #define EMAC_TX_PL0_REG     (0x18)
  71. #define EMAC_TX_PL1_REG     (0x1c)
  72. #define EMAC_TX_STA_REG     (0x20)
  73. #define EMAC_TX_IO_DATA_REG (0x24)
  74. #define EMAC_TX_IO_DATA1_REG    (0x28)
  75. #define EMAC_TX_TSVL0_REG   (0x2c)
  76. #define EMAC_TX_TSVH0_REG   (0x30)
  77. #define EMAC_TX_TSVL1_REG   (0x34)
  78. #define EMAC_TX_TSVH1_REG   (0x38)
  79.  
  80. #define EMAC_RX_CTL_REG     (0x3c)
  81. #define EMAC_RX_HASH0_REG   (0x40)
  82. #define EMAC_RX_HASH1_REG   (0x44)
  83. #define EMAC_RX_STA_REG     (0x48)
  84. #define EMAC_RX_IO_DATA_REG (0x4c)
  85. #define EMAC_RX_FBC_REG     (0x50)
  86.  
  87. #define EMAC_INT_CTL_REG    (0x54)
  88. #define EMAC_INT_STA_REG    (0x58)
  89.  
  90. #define EMAC_MAC_CTL0_REG   (0x5c)
  91. #define EMAC_MAC_CTL1_REG   (0x60)
  92. #define EMAC_MAC_IPGT_REG   (0x64)
  93. #define EMAC_MAC_IPGR_REG   (0x68)
  94. #define EMAC_MAC_CLRT_REG   (0x6c)
  95. #define EMAC_MAC_MAXF_REG   (0x70)
  96. #define EMAC_MAC_SUPP_REG   (0x74)
  97. #define EMAC_MAC_TEST_REG   (0x78)
  98. #define EMAC_MAC_MCFG_REG   (0x7c)
  99. #define EMAC_MAC_A0_REG     (0x98)
  100. #define EMAC_MAC_A1_REG     (0x9c)
  101. #define EMAC_MAC_A2_REG     (0xa0)
  102.  
  103. #define EMAC_SAFX_L_REG0    (0xa4)
  104. #define EMAC_SAFX_H_REG0    (0xa8)
  105. #define EMAC_SAFX_L_REG1    (0xac)
  106. #define EMAC_SAFX_H_REG1    (0xb0)
  107. #define EMAC_SAFX_L_REG2    (0xb4)
  108. #define EMAC_SAFX_H_REG2    (0xb8)
  109. #define EMAC_SAFX_L_REG3    (0xbc)
  110. #define EMAC_SAFX_H_REG3    (0xc0)
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