20141009_KUAS_Verilog_SyynchoronousCounter_Mod24

/*******************************************/
/** 20141009 SyynchoronousCounter (Mod24) **/
/** Maker  : Yan                          **/
/** E-Mail : [email protected]        **/
/** Date   : 2014/10/09 pm.10:15          **/
/*******************************************/

module SyynchoronousCounter_Mod24(Clk, reset, _output);
    input       Clk, reset;
    output reg  [4:0]   _output;

    always @(negedge Clk)
    begin
        if(reset == 0)
        begin
            if(_output == 23)
            begin
                _output = 0;
            end
            else if(_output < 23)
            begin
                _output = _output + 1;
            end
        end
        else if(reset == 1)
        begin
            _output = 0;
        end
    end
endmodule