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shihabsikder

8 bit comperator

Jan 7th, 2021
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  1. --Shihab Sikder
  2. --ID: 180041132
  3. --Section: A
  4.  
  5. library IEEE;
  6. use IEEE.STD_LOGIC_1164.ALL;
  7.  
  8. entity comparator is
  9. port (
  10.       clock: in std_logic;
  11.       M,N: in std_logic_vector(7 downto 0);
  12.       IAB: in std_logic;
  13.       Output: out std_logic
  14.  );
  15. end comparator;
  16. architecture Behavioral of comparator is
  17. signal AB: std_logic_vector(7 downto 0);
  18. signal Result: std_logic;
  19.  
  20. begin
  21.     AB(0) <= (not M(0)) xnor (not N(0));
  22.     AB(1) <= (not M(1)) xnor (not N(1));
  23.     AB(2) <= (not M(2)) xnor (not N(2));
  24.     AB(3) <= (not M(3)) xnor (not N(3));
  25.     AB(4) <= (not M(4)) xnor (not N(4));
  26.     AB(5) <= (not M(5)) xnor (not N(5));
  27.     AB(6) <= (not M(6)) xnor (not N(6));
  28.     AB(7) <= (not M(7)) xnor (not N(7));
  29.    
  30.     process(clock)
  31.     begin
  32.     if(rising_edge(clock))then
  33.         if(AB = x"FF" and IAB='0')then
  34.             Result<='000';
  35.         else
  36.             Result = IAB;
  37.         end if;
  38.     end if;
  39.     end process;
  40.     output<=Result;
  41. end Behavioral;
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