8 bit comperator

--Shihab Sikder
--ID: 180041132
--Section: A

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
port (
      clock: in std_logic;
      M,N: in std_logic_vector(7 downto 0);
      IAB: in std_logic;
      Output: out std_logic
 );
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0);
signal Result: std_logic;

begin
    AB(0) <= (not M(0)) xnor (not N(0));
    AB(1) <= (not M(1)) xnor (not N(1));
    AB(2) <= (not M(2)) xnor (not N(2));
    AB(3) <= (not M(3)) xnor (not N(3));
    AB(4) <= (not M(4)) xnor (not N(4));
    AB(5) <= (not M(5)) xnor (not N(5));
    AB(6) <= (not M(6)) xnor (not N(6));
    AB(7) <= (not M(7)) xnor (not N(7));

    process(clock)
    begin
    if(rising_edge(clock))then
        if(AB = x"FF" and IAB='0')then
            Result<='000';
        else
            Result = IAB;
        end if;
    end if;
    end process;
    output<=Result;
end Behavioral;