library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity sum8bit is
   generic (N: natural := 8);
    Port ( COUT : out  STD_LOGIC;
           CIN : in  STD_LOGIC;
           x0 : in  STD_LOGIC_VECTOR (7 downto 0);
           x1 : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end sum8bit;

architecture Behavioral of sum8bit is

component sum1bit is
    Port ( CIN : in  STD_LOGIC;
           x0 : in  STD_LOGIC;
           x1 : in  STD_LOGIC;
           COUT : out  STD_LOGIC;
           y : out  STD_LOGIC);
end component;

signal tmp:STD_LOGIC_VECTOR (N-1  downto 0);

begin
g: for i in 0 to N-1 generate
    i0: if i = 0 generate
        S0: sum1bit port map (CIN => CIN, x0 => x0(i), x1 => x1(i), COUT => tmp(i), y => y(i));
    end generate i0;
    ina: if i > 0 and i < N-1 generate
        SN: sum1bit port map (CIN => tmp(i-1), x0 => x0(i), x1 => x1(i), COUT => tmp(i), y => y(i));
    end generate ina;
    in1: if i = N-1 generate
        S7: sum1bit port map (CIN => tmp(i-1), x0 => x0(i), x1 => x1(i), COUT => COUT, y => y(i));
    end generate in1;

end generate g;

end Behavioral;