library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gownowkiblu is
    generic(
        granica_gorna : std_logic_vector(7 downto 0):= "00000010";
        granica_dolna : std_logic_vector(7 downto 0):= "00000000"
    );
    port(
        wartosc : out std_logic_vector(7 downto 0);
        reset : in std_logic;
        kierunek : in std_logic;
        clk : in std_logic
    );
end gownowkiblu;

architecture witamwszystkiepolskiekurwy of gownowkiblu is
    signal wartosc_buforowana : std_logic_vector(7 downto 0):=granica_dolna;
begin
    process(clk, reset, kierunek) begin
        case kierunek is
            when '1' =>
                if(reset = '1') then
                    wartosc_buforowana <= granica_dolna;
                elsif(rising_edge(clk)) then
                    if(wartosc_buforowana = granica_gorna) then
                        wartosc_buforowana <= granica_dolna;
                    else
                        wartosc_buforowana <= std_logic_vector( unsigned(wartosc_buforowana) + 1 );
                    end if;
                end if;
            when '0' =>
                if(reset = '1') then
                    wartosc_buforowana <= granica_gorna;
                elsif(rising_edge(clk)) then
                    if(wartosc_buforowana = granica_dolna) then
                        wartosc_buforowana <= granica_gorna;
                    else
                        wartosc_buforowana <= std_logic_vector( unsigned(wartosc_buforowana) - 1 );
                    end if;
                end if;
             when others =>
        end case;
    end process;
    wartosc <= wartosc_buforowana;
end witamwszystkiepolskiekurwy;