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  1. f/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
  2. /*
  3.  * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
  4.  * Author: STM32CubeMX code generation for STMicroelectronics.
  5.  */
  6.  
  7. /dts-v1/;
  8. #include "stm32mp157c.dtsi"
  9. #include "stm32mp157c-m4-srm.dtsi"
  10. #include "stm32mp157cab-pinctrl.dtsi"
  11.  
  12. /* USER CODE BEGIN includes */
  13. #include "stm32mp153a-raichu-cubemx-mx-u-boot.dtsi"
  14. #include <dt-bindings/gpio/gpio.h>
  15. #include <dt-bindings/input/input.h>
  16. #include <dt-bindings/mfd/st,stpmic1.h>
  17. #include <dt-bindings/rtc/rtc-stm32.h>
  18. /* USER CODE END includes */
  19.  
  20. / {
  21.     model = "STMicroelectronics custom STM32CubeMX board";
  22.     compatible = "st,stm32mp153a-raichu-cubemx-mx", "st,stm32mp153";
  23.  
  24.     memory@c0000000 {
  25.         reg = <0xc0000000 0x10000000>;
  26.  
  27.         /* USER CODE BEGIN memory */
  28.         /* USER CODE END memory */
  29.     };
  30.  
  31.     reserved-memory {
  32.         #address-cells = <1>;
  33.         #size-cells = <1>;
  34.         ranges;
  35.  
  36.         /* USER CODE BEGIN reserved-memory */
  37.         retram: retram@0x38000000 {
  38.             compatible = "shared-dma-pool";
  39.             reg = <0x38000000 0x10000>;
  40.             no-map;
  41.         };
  42.  
  43.         mcuram: mcuram@0x30000000 {
  44.             compatible = "shared-dma-pool";
  45.             reg = <0x30000000 0x40000>;
  46.             no-map;
  47.         };
  48.  
  49.         mcuram2: mcuram2@0x10000000 {
  50.             compatible = "shared-dma-pool";
  51.             reg = <0x10000000 0x40000>;
  52.             no-map;
  53.         };
  54.  
  55.         vdev0vring0: vdev0vring0@10040000 {
  56.             compatible = "shared-dma-pool";
  57.             reg = <0x10040000 0x2000>;
  58.             no-map;
  59.         };
  60.  
  61.         vdev0vring1: vdev0vring1@10042000 {
  62.             compatible = "shared-dma-pool";
  63.             reg = <0x10042000 0x2000>;
  64.             no-map;
  65.         };
  66.  
  67.         vdev0buffer: vdev0buffer@10044000 {
  68.             compatible = "shared-dma-pool";
  69.             reg = <0x10044000 0x4000>;
  70.             no-map;
  71.         };
  72.         /* USER CODE END reserved-memory */
  73.  
  74.         gpu_reserved: gpu@ce000000 {
  75.             reg = <0xce000000 0x2000000>;
  76.             no-map;
  77.         };
  78.     };
  79.  
  80.     /* USER CODE BEGIN root */
  81.     chosen {
  82.         stdout-path = "serial0:115200n8";
  83.     };
  84.  
  85.     aliases {
  86.         serial0 = &uart4;
  87.         ethernet0 = &ethernet0;
  88.     };
  89.  
  90.     sram: sram@10050000 {
  91.         compatible = "mmio-sram";
  92.         reg = <0x10050000 0x10000>;
  93.         #address-cells = <1>;
  94.         #size-cells = <1>;
  95.         ranges = <0 0x10050000 0x10000>;
  96.  
  97.         dma_pool: dma_pool@0 {
  98.             reg = <0x0 0x10000>;
  99.             pool;
  100.         };
  101.     };
  102.  
  103.     sd_switch: regulator-sd_switch {
  104.         compatible = "regulator-gpio";
  105.         regulator-name = "sd_switch";
  106.         regulator-min-microvolt = <1800000>;
  107.         regulator-max-microvolt = <2900000>;
  108.         regulator-type = "voltage";
  109.         regulator-always-on;
  110.  
  111.         gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
  112.         gpios-states = <0>;
  113.         states = <1800000 0x1 2900000 0x0>;
  114.     };
  115.  
  116.     usb_phy_tuning: usb-phy-tuning {
  117.         st,hs-dc-level = <2>;
  118.         st,fs-rftime-tuning;
  119.         st,hs-rftime-reduction;
  120.         st,hs-current-trim = <15>;
  121.         st,hs-impedance-trim = <1>;
  122.         st,squelch-level = <3>;
  123.         st,hs-rx-offset = <2>;
  124.         st,no-lsfs-sc;
  125.     };
  126.     /* USER CODE END root */
  127.  
  128.     clocks {
  129.         /* USER CODE BEGIN clocks */
  130.         /* USER CODE END clocks */
  131.  
  132.         clk_lsi: clk-lsi {
  133.             clock-frequency = <32000>;
  134.         };
  135.  
  136.         clk_hsi: clk-hsi {
  137.             clock-frequency = <64000000>;
  138.         };
  139.  
  140.         clk_lse: clk-lse {
  141.             clock-frequency = <32768>;
  142.         };
  143.  
  144.         clk_hse: clk-hse {
  145.             clock-frequency = <24000000>;
  146.         };
  147.     };
  148.  
  149. }; /*root*/
  150.  
  151. &pinctrl {
  152.     u-boot,dm-pre-reloc;
  153.  
  154.     adc_pins_mx: adc_mx-0 {
  155.         pins {
  156.             pinmux = <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
  157.                      <STM32_PINMUX('A', 4, ANALOG)>; /* ADC1_INP18 */
  158.         };
  159.     };
  160.  
  161.     adc_sleep_pins_mx: adc_sleep_mx-0 {
  162.         pins {
  163.             pinmux = <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
  164.                      <STM32_PINMUX('A', 4, ANALOG)>; /* ADC1_INP18 */
  165.         };
  166.     };
  167.  
  168.     eth1_pins_mx: eth1_mx-0 {
  169.         pins1 {
  170.             pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_REF_CLK */
  171.                      <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
  172.                      <STM32_PINMUX('G', 8, AF2)>, /* ETH1_CLK */
  173.                      <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
  174.                      <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
  175.             bias-disable;
  176.             drive-push-pull;
  177.             slew-rate = <1>;
  178.         };
  179.         pins2 {
  180.             pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
  181.             bias-disable;
  182.             drive-push-pull;
  183.             slew-rate = <0>;
  184.         };
  185.         pins3 {
  186.             pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
  187.                      <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
  188.                      <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RXD1 */
  189.                      <STM32_PINMUX('G', 12, AF11)>; /* ETH1_PHY_INTN */
  190.             bias-disable;
  191.         };
  192.         pins4 {
  193.             pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
  194.         };
  195.     };
  196.  
  197.     eth1_sleep_pins_mx: eth1_sleep_mx-0 {
  198.         pins {
  199.             pinmux = <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_REF_CLK */
  200.                      <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
  201.                      <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
  202.                      <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
  203.                      <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
  204.                      <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
  205.                      <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
  206.                      <STM32_PINMUX('G', 8, ANALOG)>, /* ETH1_CLK */
  207.                      <STM32_PINMUX('G', 12, ANALOG)>, /* ETH1_PHY_INTN */
  208.                      <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
  209.                      <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
  210.         };
  211.     };
  212.  
  213.     fdcan2_pins_mx: fdcan2_mx-0 {
  214.         pins1 {
  215.             pinmux = <STM32_PINMUX('B', 12, AF9)>; /* FDCAN2_RX */
  216.             bias-disable;
  217.         };
  218.         pins2 {
  219.             pinmux = <STM32_PINMUX('B', 13, AF9)>; /* FDCAN2_TX */
  220.             bias-disable;
  221.             drive-push-pull;
  222.             slew-rate = <0>;
  223.         };
  224.     };
  225.  
  226.     fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 {
  227.         pins {
  228.             pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* FDCAN2_RX */
  229.                      <STM32_PINMUX('B', 13, ANALOG)>; /* FDCAN2_TX */
  230.         };
  231.     };
  232.  
  233.     fmc_pins_mx: fmc_mx-0 {
  234.         u-boot,dm-pre-reloc;
  235.         pins1 {
  236.             u-boot,dm-pre-reloc;
  237.             pinmux = <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  238.                      <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  239.                      <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  240.                      <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  241.                      <STM32_PINMUX('D', 11, AF12)>, /* FMC_CLE */
  242.                      <STM32_PINMUX('D', 12, AF12)>, /* FMC_ALE */
  243.                      <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  244.                      <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  245.                      <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  246.                      <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  247.                      <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  248.                      <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  249.                      <STM32_PINMUX('G', 9, AF12)>; /* FMC_NCE */
  250.             bias-disable;
  251.             drive-push-pull;
  252.             slew-rate = <1>;
  253.         };
  254.         pins2 {
  255.             u-boot,dm-pre-reloc;
  256.             pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
  257.             bias-pull-up;
  258.         };
  259.     };
  260.  
  261.     fmc_sleep_pins_mx: fmc_sleep_mx-0 {
  262.         u-boot,dm-pre-reloc;
  263.         pins {
  264.             u-boot,dm-pre-reloc;
  265.             pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
  266.                      <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
  267.                      <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
  268.                      <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
  269.                      <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
  270.                      <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_CLE */
  271.                      <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_ALE */
  272.                      <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
  273.                      <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
  274.                      <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
  275.                      <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
  276.                      <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
  277.                      <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
  278.                      <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NCE */
  279.         };
  280.     };
  281.  
  282.     i2c4_pins_mx: i2c4_mx-0 {
  283.         u-boot,dm-pre-reloc;
  284.         pins {
  285.             u-boot,dm-pre-reloc;
  286.             pinmux = <STM32_PINMUX('B', 6, AF6)>, /* I2C4_SCL */
  287.                  <STM32_PINMUX('D', 13, AF4)>; /* I2C4_SDA */
  288.             bias-disable;
  289.             drive-open-drain;
  290.             slew-rate = <0>;
  291.         };
  292.     };
  293.  
  294.     i2c4_sleep_pins_mx: i2c4_sleep_mx-0 {
  295.         u-boot,dm-pre-reloc;
  296.         pins {
  297.             u-boot,dm-pre-reloc;
  298.             pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* I2C4_SCL */
  299.                  <STM32_PINMUX('D', 13, ANALOG)>; /* I2C4_SDA */
  300.         };
  301.     };
  302.  
  303.     spi2_pins_mx: spi2_mx-0 {
  304.         pins {
  305.             pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
  306.                      <STM32_PINMUX('C', 2, AF5)>, /* SPI2_MISO */
  307.                      <STM32_PINMUX('C', 3, AF5)>; /* SPI2_MOSI */
  308.             bias-disable;
  309.             drive-push-pull;
  310.             slew-rate = <1>;
  311.         };
  312.     };
  313.  
  314.     spi2_sleep_pins_mx: spi2_sleep_mx-0 {
  315.         pins {
  316.             pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
  317.                      <STM32_PINMUX('C', 2, ANALOG)>, /* SPI2_MISO */
  318.                      <STM32_PINMUX('C', 3, ANALOG)>; /* SPI2_MOSI */
  319.         };
  320.     };
  321.  
  322.     spi3_pins_mx: spi3_mx-0 {
  323.         pins {
  324.             pinmux = <STM32_PINMUX('A', 8, AF5)>, /* SPI3_MOSI */
  325.                      <STM32_PINMUX('B', 3, AF6)>, /* SPI3_SCK */
  326.                      <STM32_PINMUX('B', 4, AF6)>; /* SPI3_MISO */
  327.             bias-disable;
  328.             drive-push-pull;
  329.             slew-rate = <1>;
  330.         };
  331.     };
  332.  
  333.     spi3_sleep_pins_mx: spi3_sleep_mx-0 {
  334.         pins {
  335.             pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SPI3_MOSI */
  336.                      <STM32_PINMUX('B', 3, ANALOG)>, /* SPI3_SCK */
  337.                      <STM32_PINMUX('B', 4, ANALOG)>; /* SPI3_MISO */
  338.         };
  339.     };
  340.  
  341.     tim1_pwm_pins_mx: tim1_pwm_mx-0 {
  342.         pins {
  343.             pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
  344.             bias-disable;
  345.             drive-push-pull;
  346.             slew-rate = <0>;
  347.         };
  348.     };
  349.  
  350.     tim1_pwm_sleep_pins_mx: tim1_pwm_sleep_mx-0 {
  351.         pins {
  352.             pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
  353.         };
  354.     };
  355.  
  356.     tim3_pwm_pins_mx: tim3_pwm_mx-0 {
  357.         pins {
  358.             pinmux = <STM32_PINMUX('C', 7, AF2)>, /* TIM3_CH2 */
  359.                      <STM32_PINMUX('C', 8, AF2)>, /* TIM3_CH3 */
  360.                      <STM32_PINMUX('C', 9, AF2)>; /* TIM3_CH4 */
  361.             bias-disable;
  362.             drive-push-pull;
  363.             slew-rate = <0>;
  364.         };
  365.     };
  366.  
  367.     tim3_pwm_sleep_pins_mx: tim3_pwm_sleep_mx-0 {
  368.         pins {
  369.             pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* TIM3_CH2 */
  370.                      <STM32_PINMUX('C', 8, ANALOG)>, /* TIM3_CH3 */
  371.                      <STM32_PINMUX('C', 9, ANALOG)>; /* TIM3_CH4 */
  372.         };
  373.     };
  374.  
  375.     uart4_pins_mx: uart4_mx-0 {
  376.         u-boot,dm-pre-reloc;
  377.         pins1 {
  378.             u-boot,dm-pre-reloc;
  379.             pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
  380.             bias-disable;
  381.         };
  382.         pins2 {
  383.             u-boot,dm-pre-reloc;
  384.             pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
  385.             bias-disable;
  386.             drive-push-pull;
  387.             slew-rate = <0>;
  388.         };
  389.     };
  390.  
  391.     uart4_sleep_pins_mx: uart4_sleep_mx-0 {
  392.         u-boot,dm-pre-reloc;
  393.         pins {
  394.             u-boot,dm-pre-reloc;
  395.             pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* UART4_RX */
  396.                      <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
  397.         };
  398.     };
  399.  
  400.     uart5_pins_mx: uart5_mx-0 {
  401.         pins1 {
  402.             pinmux = <STM32_PINMUX('C', 12, AF8)>; /* UART5_TX */
  403.             bias-disable;
  404.             drive-push-pull;
  405.             slew-rate = <0>;
  406.         };
  407.         pins2 {
  408.             pinmux = <STM32_PINMUX('D', 2, AF8)>; /* UART5_RX */
  409.             bias-disable;
  410.         };
  411.     };
  412.  
  413.     uart5_sleep_pins_mx: uart5_sleep_mx-0 {
  414.         pins {
  415.             pinmux = <STM32_PINMUX('C', 12, ANALOG)>, /* UART5_TX */
  416.                      <STM32_PINMUX('D', 2, ANALOG)>; /* UART5_RX */
  417.         };
  418.     };
  419.  
  420.     uart7_pins_mx: uart7_mx-0 {
  421.         pins1 {
  422.             pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
  423.             bias-disable;
  424.         };
  425.         pins2 {
  426.             pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
  427.             bias-disable;
  428.             drive-push-pull;
  429.             slew-rate = <0>;
  430.         };
  431.     };
  432.  
  433.     uart7_sleep_pins_mx: uart7_sleep_mx-0 {
  434.         pins {
  435.             pinmux = <STM32_PINMUX('F', 6, ANALOG)>, /* UART7_RX */
  436.                      <STM32_PINMUX('F', 7, ANALOG)>; /* UART7_TX */
  437.         };
  438.     };
  439.  
  440.     uart8_pins_mx: uart8_mx-0 {
  441.         pins1 {
  442.             pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
  443.             bias-disable;
  444.         };
  445.         pins2 {
  446.             pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
  447.             bias-disable;
  448.             drive-push-pull;
  449.             slew-rate = <0>;
  450.         };
  451.     };
  452.  
  453.     uart8_sleep_pins_mx: uart8_sleep_mx-0 {
  454.         pins {
  455.             pinmux = <STM32_PINMUX('E', 0, ANALOG)>, /* UART8_RX */
  456.                      <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
  457.         };
  458.     };
  459.  
  460.     usb_otg_hs_pins_mx: usb_otg_hs_mx-0 {
  461.         pins {
  462.             pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
  463.         };
  464.     };
  465.  
  466.     usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 {
  467.         pins {
  468.             pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
  469.         };
  470.     };
  471.  
  472.     /* USER CODE BEGIN pinctrl */
  473.     /* USER CODE END pinctrl */
  474. };
  475.  
  476. &pinctrl_z {
  477.     u-boot,dm-pre-reloc;
  478.  
  479.     /* USER CODE BEGIN pinctrl_z */
  480.     /* USER CODE END pinctrl_z */
  481. };
  482.  
  483. &m4_rproc{
  484.     mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
  485.     mbox-names = "vq0", "vq1", "shutdown";
  486.     recovery;
  487.     status = "okay";
  488.  
  489.     /* USER CODE BEGIN m4_rproc */
  490.     interrupt-parent = <&exti>;
  491.     interrupts = <68 1>;
  492.     interrupt-names = "wdg";
  493.     /* USER CODE END m4_rproc */
  494.  
  495.     m4_system_resources{
  496.         status = "okay";
  497.  
  498.         /* USER CODE BEGIN m4_system_resources */
  499.         /* USER CODE END m4_system_resources */
  500.     };
  501. };
  502.  
  503. &adc{
  504.     pinctrl-names = "default", "sleep";
  505.     pinctrl-0 = <&adc_pins_mx>;
  506.     pinctrl-1 = <&adc_sleep_pins_mx>;
  507.     status = "okay";
  508.  
  509.     /* USER CODE BEGIN adc */
  510.     /* USER CODE END adc */
  511. };
  512.  
  513. &bsec{
  514.     status = "okay";
  515.  
  516.     /* USER CODE BEGIN bsec */
  517.     /* USER CODE END bsec */
  518. };
  519.  
  520. &dts{
  521.     status = "okay";
  522.  
  523.     /* USER CODE BEGIN dts */
  524.     /* USER CODE END dts */
  525. };
  526.  
  527. &ethernet0{
  528.     pinctrl-names = "default", "sleep";
  529.     pinctrl-0 = <&eth1_pins_mx>;
  530.     pinctrl-1 = <&eth1_sleep_pins_mx>;
  531.     status = "okay";
  532.  
  533.     /* USER CODE BEGIN ethernet0 */
  534.     mac-address = [df921222a51c];
  535.     phy-mode = "rmii";
  536.     max-speed = <100>;
  537.     phy-handle = <&phy0>;
  538.     st,eth_ref_clk_sel;
  539.     snps,reset-active-low;
  540.     snps,reset-delays-us = <0>, <10000>, <1000000>;
  541.     snps,reset-gpio = <&gpiob 0 GPIO_ACTIVE_HIGH>;
  542.  
  543.     clock-names = "stmmaceth",
  544.             "mac-clk-tx",
  545.             "mac-clk-rx",
  546.             "eth-ck",
  547.             "syscfg-clk",
  548.             "ethstp";
  549.     clocks = <&rcc ETHMAC>,
  550.             <&rcc ETHTX>,
  551.             <&rcc ETHRX>,
  552.             <&rcc ETHCK_K>,
  553.             <&rcc SYSCFG>,
  554.             <&rcc ETHSTP>;
  555.  
  556.     mdio0 {
  557.         #address-cells = <1>;
  558.         #size-cells = <0>;
  559.         compatible = "snps,dwmac-mdio";
  560.         phy0: ethernet-phy@3 {
  561.             reg = <3>;
  562.         };
  563.     };
  564.     /* USER CODE END ethernet0 */
  565. };
  566.  
  567. &fmc{
  568.     u-boot,dm-pre-reloc;
  569.     pinctrl-names = "default", "sleep";
  570.     pinctrl-0 = <&fmc_pins_mx>;
  571.     pinctrl-1 = <&fmc_sleep_pins_mx>;
  572.     status = "okay";
  573.  
  574.     /* USER CODE BEGIN fmc */
  575.     #address-cells = <1>;
  576.     #size-cells = <0>;
  577.  
  578.     nand: nand@0 {
  579.         reg = <0>;
  580.         nand-on-flash-bbt;
  581.         #address-cells = <1>;
  582.         #size-cells = <1>;
  583.     };
  584.     /* USER CODE END fmc */
  585. };
  586.  
  587. &hsem{
  588.     status = "okay";
  589.  
  590.     /* USER CODE BEGIN hsem */
  591.     /* USER CODE END hsem */
  592. };
  593.  
  594. &i2c4{
  595.     u-boot,dm-pre-reloc;
  596.     pinctrl-names = "default", "sleep";
  597.     pinctrl-0 = <&i2c4_pins_mx>;
  598.     pinctrl-1 = <&i2c4_sleep_pins_mx>;
  599.     status = "okay";
  600.  
  601.     /* USER CODE BEGIN i2c4 */
  602.     i2c-scl-rising-time-ns = <185>;
  603.     i2c-scl-falling-time-ns = <20>;
  604.     /delete-property/dmas;
  605.     /delete-property/dma-names;
  606.  
  607.  
  608.     pmic: stpmic@33 {
  609.         compatible = "st,stpmic1";
  610.         reg = <0x33>;
  611.         interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  612.         interrupt-controller;
  613.         #interrupt-cells = <2>;
  614.         status = "okay";
  615.  
  616.         st,main-control-register = <0x04>;
  617.         st,vin-control-register = <0xc0>;
  618.         st,usb-control-register = <0x20>;
  619.  
  620.         regulators {
  621.             compatible = "st,stpmic1-regulators";
  622.  
  623.             ldo1-supply = <&v3v3>;
  624.             ldo3-supply = <&vdd_ddr>;
  625.             ldo6-supply = <&v3v3>;
  626.             pwr_sw1-supply = <&bst_out>;
  627.             pwr_sw2-supply = <&bst_out>;
  628.  
  629.             vddcore: buck1 {
  630.                 regulator-name = "vddcore";
  631.                 regulator-min-microvolt = <1200000>;
  632.                 regulator-max-microvolt = <1350000>;
  633.                 regulator-always-on;
  634.                 regulator-initial-mode = <0>;
  635.                 regulator-over-current-protection;
  636.             };
  637.  
  638.             vdd_ddr: buck2 {
  639.                 regulator-name = "vdd_ddr";
  640.                 regulator-min-microvolt = <1350000>;
  641.                 regulator-max-microvolt = <1350000>;
  642.                 regulator-always-on;
  643.                 regulator-initial-mode = <0>;
  644.                 regulator-over-current-protection;
  645.             };
  646.  
  647.             vdd: buck3 {
  648.                 regulator-name = "vdd";
  649.                 regulator-min-microvolt = <3300000>;
  650.                 regulator-max-microvolt = <3300000>;
  651.                 regulator-always-on;
  652.                 st,mask-reset;
  653.                 regulator-initial-mode = <0>;
  654.                 regulator-over-current-protection;
  655.             };
  656.  
  657.             v3v3: buck4 {
  658.                 regulator-name = "v3v3";
  659.                 regulator-min-microvolt = <3300000>;
  660.                 regulator-max-microvolt = <3300000>;
  661.                 regulator-always-on;
  662.                 regulator-over-current-protection;
  663.                 regulator-initial-mode = <0>;
  664.             };
  665.  
  666.             vtt_ddr: ldo3 {
  667.                 regulator-name = "vtt_ddr";
  668.                 regulator-min-microvolt = <500000>;
  669.                 regulator-max-microvolt = <750000>;
  670.                 regulator-always-on;
  671.                 regulator-over-current-protection;
  672.             };
  673.  
  674.             vdda: ldo5 {
  675.                 regulator-name = "vdda";
  676.                 regulator-min-microvolt = <3300000>;
  677.                 regulator-max-microvolt = <3300000>;
  678.                 interrupts = <IT_CURLIM_LDO5 0>;
  679.                 regulator-always-on;
  680.             };
  681.  
  682.             vref_ddr: vref_ddr {
  683.                 regulator-name = "vref_ddr";
  684.                 regulator-always-on;
  685.                 regulator-over-current-protection;
  686.             };
  687.  
  688.              bst_out: boost {
  689.                 regulator-name = "bst_out";
  690.                 interrupts = <IT_OCP_BOOST 0>;
  691.              };
  692.  
  693.             vbus_otg: pwr_sw1 {
  694.                 regulator-name = "vbus_otg";
  695.                 interrupts = <IT_OCP_OTG 0>;
  696.                 regulator-active-discharge;
  697.              };
  698.  
  699.              vbus_sw: pwr_sw2 {
  700.                 regulator-name = "vbus_sw";
  701.                 interrupts = <IT_OCP_SWOUT 0>;
  702.                 regulator-active-discharge;
  703.              };
  704.         };
  705.  
  706.         onkey {
  707.             compatible = "st,stpmic1-onkey";
  708.             interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
  709.             interrupt-names = "onkey-falling", "onkey-rising";
  710.             status = "okay";
  711.         };
  712.  
  713.         watchdog {
  714.             compatible = "st,stpmic1-wdt";
  715.             status = "disabled";
  716.         };
  717.     };
  718.     /* USER CODE END i2c4 */
  719. };
  720.  
  721. &ipcc{
  722.     status = "okay";
  723.  
  724.     /* USER CODE BEGIN ipcc */
  725.     /* USER CODE END ipcc */
  726. };
  727.  
  728. &iwdg2{
  729.     status = "disabled";
  730.  
  731.     /* USER CODE BEGIN iwdg2 */
  732.     timeout-sec = <32>;
  733.     /* USER CODE END iwdg2 */
  734. };
  735.  
  736. &m_can2{
  737.     pinctrl-names = "default", "sleep";
  738.     pinctrl-0 = <&fdcan2_pins_mx>;
  739.     pinctrl-1 = <&fdcan2_sleep_pins_mx>;
  740.     status = "okay";
  741.  
  742.     /* USER CODE BEGIN m_can2 */
  743.     /* USER CODE END m_can2 */
  744. };
  745.  
  746. &timers6{
  747.     status = "okay";
  748.  
  749.     /delete-property/dmas;
  750.     /delete-property/dma-names;
  751.     timer@5 {
  752.         status = "okay";
  753.     };
  754. };
  755.  
  756. &m4_timers1{
  757.     pinctrl-names = "rproc_default";
  758.     pinctrl-0 = <&tim1_pwm_pins_mx>;
  759.     status = "okay";
  760.  
  761.     /* USER CODE BEGIN m4_timers1 */
  762.     /* USER CODE END m4_timers1 */
  763. };
  764.  
  765. &m4_timers3{
  766.     pinctrl-names = "rproc_default";
  767.     pinctrl-0 = <&tim3_pwm_pins_mx>;
  768.     status = "okay";
  769.  
  770.     /* USER CODE BEGIN m4_timers3 */
  771.     /* USER CODE END m4_timers3 */
  772. };
  773.  
  774. &pwr{
  775.     status = "okay";
  776.  
  777.     /* USER CODE BEGIN pwr */
  778.     pwr-regulators {
  779.         vdd-supply = <&vdd>;
  780.         vdd_3v3_usbfs-supply = <&vdd>;
  781.     };
  782.     /* USER CODE END pwr */
  783. };
  784.  
  785. &rcc{
  786.     u-boot,dm-pre-reloc;
  787.     status = "okay";
  788.  
  789.     /* USER CODE BEGIN rcc */
  790.     /* USER CODE END rcc */
  791. };
  792.  
  793. &rng1{
  794.     status = "okay";
  795.  
  796.     /* USER CODE BEGIN rng1 */
  797.     /* USER CODE END rng1 */
  798. };
  799.  
  800. &rtc{
  801.     status = "okay";
  802.  
  803.     /* USER CODE BEGIN rtc */
  804.     /* USER CODE END rtc */
  805. };
  806.  
  807. &spi2{
  808.     pinctrl-names = "default", "sleep";
  809.     pinctrl-0 = <&spi2_pins_mx>;
  810.     pinctrl-1 = <&spi2_sleep_pins_mx>;
  811.     status = "okay";
  812.  
  813.     /* USER CODE BEGIN spi2 */
  814.     /* USER CODE END spi2 */
  815. };
  816.  
  817. &spi3{
  818.     pinctrl-names = "default", "sleep";
  819.     pinctrl-0 = <&spi3_pins_mx>;
  820.     pinctrl-1 = <&spi3_sleep_pins_mx>;
  821.     status = "okay";
  822.  
  823.     /* USER CODE BEGIN spi3 */
  824.     /* USER CODE END spi3 */
  825. };
  826.  
  827. &timers6{
  828.     status = "okay";
  829.  
  830.     /* USER CODE BEGIN timers6 */
  831.     /* USER CODE END timers6 */
  832. };
  833.  
  834. &uart4{
  835.     u-boot,dm-pre-reloc;
  836.     pinctrl-names = "default", "sleep";
  837.     pinctrl-0 = <&uart4_pins_mx>;
  838.     pinctrl-1 = <&uart4_sleep_pins_mx>;
  839.     status = "okay";
  840.  
  841.     /* USER CODE BEGIN uart4 */
  842.     /* USER CODE END uart4 */
  843. };
  844.  
  845. &uart5{
  846.     pinctrl-names = "default", "sleep";
  847.     pinctrl-0 = <&uart5_pins_mx>;
  848.     pinctrl-1 = <&uart5_sleep_pins_mx>;
  849.     status = "okay";
  850.  
  851.     /* USER CODE BEGIN uart5 */
  852.     /* USER CODE END uart5 */
  853. };
  854.  
  855. &uart7{
  856.     pinctrl-names = "default", "sleep";
  857.     pinctrl-0 = <&uart7_pins_mx>;
  858.     pinctrl-1 = <&uart7_sleep_pins_mx>;
  859.     status = "okay";
  860.  
  861.     /* USER CODE BEGIN uart7 */
  862.     /* USER CODE END uart7 */
  863. };
  864.  
  865. &uart8{
  866.     pinctrl-names = "default", "sleep";
  867.     pinctrl-0 = <&uart8_pins_mx>;
  868.     pinctrl-1 = <&uart8_sleep_pins_mx>;
  869.     status = "okay";
  870.  
  871.     /* USER CODE BEGIN uart8 */
  872.     /* USER CODE END uart8 */
  873. };
  874.  
  875. &usbh_ehci{
  876.     status = "okay";
  877.  
  878.     /* USER CODE BEGIN usbh_ehci */
  879.     phys = <&usbphyc_port0>;
  880.     phy-names = "usb";
  881.     vbus-supply = <&vbus_sw>;
  882.     /* USER CODE END usbh_ehci */
  883. };
  884.  
  885. &usbh_ohci{
  886.     status = "okay";
  887.  
  888.     /* USER CODE BEGIN usbh_ohci */
  889.     phys = <&usbphyc_port0>;
  890.     phy-names = "usb";
  891.     vbus-supply = <&vbus_sw>;
  892.     /* USER CODE END usbh_ohci */
  893. };
  894.  
  895. &usbotg_hs{
  896.     pinctrl-names = "default"; /*, "sleep";*/
  897.     pinctrl-0 = <&usb_otg_hs_pins_mx>;
  898.     /*pinctrl-1 = <&usb_otg_hs_sleep_pins_mx>;*/
  899.     status = "okay";
  900.  
  901.     /* USER CODE BEGIN usbotg_hs */
  902.     /*dr_mode = "peripheral";*/
  903.     phys = <&usbphyc_port1 0>;
  904.     phy-names = "usb2-phy";
  905.     vbus-supply = <&vbus_otg>;
  906.     /* USER CODE END usbotg_hs */
  907. };
  908.  
  909. &usbphyc{
  910.     status = "okay";
  911.  
  912.     /* USER CODE BEGIN usbphyc */
  913.     vdd3v3-supply = <&vdd>;
  914.     /* USER CODE END usbphyc */
  915. };
  916.  
  917. &usbphyc_port0{
  918.     status = "okay";
  919.  
  920.     /* USER CODE BEGIN usbphyc_port0 */
  921.     st,phy-tuning = <&usb_phy_tuning>;
  922.     /* USER CODE END usbphyc_port0 */
  923. };
  924.  
  925. &usbphyc_port1{
  926.     status = "okay";
  927.  
  928.     /* USER CODE BEGIN usbphyc_port1 */
  929.     st,phy-tuning = <&usb_phy_tuning>;
  930.     /* USER CODE END usbphyc_port1 */
  931. };
  932.  
  933. &vrefbuf{
  934.     status = "okay";
  935.  
  936.     /* USER CODE BEGIN vrefbuf */
  937.     regulator-min-microvolt = <2500000>;
  938.     regulator-max-microvolt = <2500000>;
  939.     vdda-supply = <&vdd>;
  940.     /* USER CODE END vrefbuf */
  941. };
  942.  
  943. /* USER CODE BEGIN addons */
  944.  
  945. &m4_rproc {
  946. memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
  947.         <&vdev0vring1>, <&vdev0buffer>;
  948. };
  949.  
  950. &dma1 {
  951.     sram = <&dma_pool>;
  952. };
  953.  
  954. &dma2 {
  955.     sram = <&dma_pool>;
  956. };
  957. /* USER CODE END addons */
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