VHDL. Reg

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Test is
    generic(
        constant init : std_logic
    );
    port (
        x : in std_logic;
        reset : in std_logic;
        clk : in std_logic;
        y : out std_logic := init -- Задание значния по умолчанию
    );
end entity Test;

architecture dataflow of Test is
begin

    proc : process (clk, reset)
    begin
        if reset = '1' then
            y <= init;
        elsif rising_edge(clk) then
            y <= x;
        end if;
    end process;

end architecture dataflow;