compnot1.vhdl

-----makefile con 160ns
--tb_bin

entity tb_bin2gray is
end entity tb_bin2gray;

architecture beh of tb_bin2gray is
component bin2gray is
 port(
 x:in bit_vector(3 downto 0);
 f:out bit_vector(3 downto 0)
);
end component bin2gray;
signal bx:bit_vector(3 downto 0):=(others =>'0');
signal lf:bit_vector(3 downto 0):=(others =>'0');
begin
uut:bin2gray
 port map(
x(0)=>bx(0),
x(1)=>bx(1),
x(2)=>bx(2),
x(3)=>bx(3),
f(0)=>lf(0),
f(1)=>lf(1),
f(2)=>lf(2),
f(3)=>lf(3)
);
process
begin
  wait for 10 ns;
  bx(0)<= '1';
  wait for 10 ns;
  bx(0)<= '0';
end process;

process
begin
  wait for 20 ns;
  bx(1) <= '1';
  wait for 20 ns;
  bx(1) <= '0';
end process;

process
begin
  wait for 40 ns;
  bx(2) <= '1';
  wait for 40 ns;
  bx(2) <= '0';
end process;

process
begin
  wait for 80 ns;
  bx(3) <= '1';
  wait for 80 ns;
  bx(3) <= '0';
end process;

end architecture beh;








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--Guerra Esquivel Angel

entity compnot1 is
    port(
        x:in bit;
        f:out bit
        );
end entity compnot1;

architecture behavioral of compnot1 is
--declaracion de componentes y senales
begin
    f <= not x; --sentencia concurrente
end architecture behavioral;

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-- tb_compnot
--Guerra Esquivel Angel

entity tb_compnot1 is
end entity tb_compnot1;

architecture behavioral of tb_compnot1 is

component compnot1 is
    port(
        x:in bit;
        f:out bit
        );
end component compnot1;

signal boton:bit:='0';
signal led:bit;

--declaracion de componentes y senales
begin
    --instancia
    uut:compnot1
    port map(
        x=>boton,
        f=>led
        );

    process
    begin
        wait for 10 ns;
        boton <= '1';
        wait for 10 ns;
        boton <= '0';
    end process;

end architecture behavioral;