LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY Lab7 IS
    PORT (
        SW : in STD_LOGIC_VECTOR(1 downto 0);
        LEDR : buffer STD_LOGIC_VECTOR(1 downto 0));
END Lab7;

ARCHITECTURE Structure OF Lab7 IS
BEGIN
    LEDR(0) <= NOT(SW(0) and LEDR(1));
    LEDR(1) <= NOT(SW(1) and LEDR(0));
END Structure;