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rtbuhler

dec_bcd.vhd

Feb 20th, 2021
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VHDL 0.71 KB | None | 0 0
  1. -- Decodificador BCD
  2.  
  3. library ieee;
  4. use ieee.std_logic_1164.all;
  5.  
  6. entity dec_bcd is
  7.     port
  8.     (
  9.         x   : in std_logic_vector(3 downto 0);
  10.         d   : out std_logic_vector(6 downto 0)
  11.     );
  12. end dec_bcd;
  13.  
  14. architecture logica of dec_bcd is
  15. begin
  16.     with x select
  17.         d <=    "1000000" when "0000",
  18.                 "1111001" when "0001",
  19.                 "0100100" when "0010",
  20.                 "0110000" when "0011",
  21.                 "0011001" when "0100",
  22.                 "0010010" when "0101",
  23.                 "0000010" when "0110",
  24.                 "1111000" when "0111",
  25.                 "0000000" when "1000",
  26.                 "0010000" when "1001",
  27.                 "0001000" when "1010",
  28.                 "0000011" when "1011",
  29.                 "1000110" when "1100",
  30.                 "0100001" when "1101",
  31.                 "0000110" when "1110",
  32.                 "0001110" when others;
  33. end logica;
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