library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Processor is
 port (
    clk: in std_logic;
   SBB: in std_logic_vector( 3 downto 0);
    SBC: in std_logic_vector( 3 downto 0);
    SBA: in std_logic_vector( 3 downto 0);
    SA: in std_logic_vector(1 downto 0);
    Sid: inout std_logic_vector(1 downto 0)
   );
end Processor;

architecture Behavioral of Processor is
    signal IR,TMP,A,B,C,D,E,F,ADh,ADl,DI: std_logic_vector(15 downto 0);
    signal PC,SP, ATMP: std_logic_vector(31 downto 0);
    signal Y, BB, BC : std_logic_vector(15 downto 0); --ALU
    signal A2: std_logic_vector(31 downto 0);
    signal hex_out1,hex_out2:std_logic_vector(6 downto 0);
begin

process(SBA,IR,Y, TMP, A,B,C,D,E,F,ADh,ADl,PC,SP,ATMP)
begin
    case(SBA) is
     when "0000" => IR <= Y;
     when "0001" => TMP <= Y;
     when "0010" => A <= Y;
     when "0011" => B <= Y;
     when "0100" => C <= Y;
     when "0101" => D <= Y;
     when "0110" => E <= Y;
     when "0111" => F <= Y;
     when "1000" => ADh <=Y;
     when "1001" => ADl <= Y;
     when "1010" => PC(31 downto 16) <= Y;
     when "1011" => SP(31 downto 16) <= Y;
     when others => ATMP(31 downto 16) <= Y;
    end case;
end process;

process(SBB,IR,BB,DI,TMP,hex_out1, A,B,C,D,E,F,ADh,ADl,PC,SP,ATMP)
begin
    case SBB is
     when "0000" => BB <= DI;
                         hex_out1 <= "0000001";
     when "0001" => BB <= IR;
                         hex_out1 <= "1001111";
     when "0010" => BB <= TMP;
                         hex_out1 <= "0010010";
     when "0011" => BB <= A;
                         hex_out1 <= "0000010";
     when "0100" => BB <= B;
                         hex_out1 <= "1100000";
     when "0101" => BB <= C;
                         hex_out1 <= "0110001";
     when "0110" => BB <= D;
                         hex_out1 <= "1000010";
     when "0111" => BB <= E;
                         hex_out1 <= "0110000";
     when "1000" => BB <= F;
                         hex_out1 <= "0111000";
     when "1001" => BB <= ADh;
                         hex_out1 <= "0000110";
     when "1010" => BB <= ADl;
                         hex_out1 <= "1001100";
     when "1011" => BB <= PC(31 downto 16);
                         hex_out1 <= "0100100";
     when "1100" => BB <= PC(15 downto 0);
                         hex_out1 <= "0100100";
     when "1101" => BB <= SP(31 downto 16);
                         hex_out1 <= "0100000";
     when "1110" => BB <= SP(15 downto 0);
                         hex_out1 <= "0100000";
     when "1111" => BB <= ATMP(31 downto 16);
                        hex_out1 <= "0100000";

    end case;
end process;

process(SBC,IR,BC,DI, TMP, A,B,C,D,E,F,ADh,ADl,PC,SP,ATMP)
begin
    case SBC is
     when "0000" => BC <= DI;
     when "0001" => BC <= IR;
     when "0010" => BC <= TMP;
     when "0011" => BC <= A;
     when "0100" => BC <= B;
     when "0101" => BC <= C;
     when "0110" => BC <= D;
     when "0111" => BC <= E;
     when "1000" => BC <= F;
     when "1001" => BC <= ADh;
     when "1010" => BC <= ADl;
     when "1011" => BC <= PC(31 downto 16);
     when "1100" => BC <= PC(15 downto 0);
     when "1101" => BC <= SP(31 downto 16);
     when "1110" => BC <= SP(15 downto 0);
     when "1111" => BC <= ATMP(31 downto 16);
    end case;
end process;

process(SA,A2,ADh,ADl,PC,SP,ATMP,hex_out2)
begin
    case SA is
     when "00" => A2(31 downto 16) <= ADh;
                      A2(15 downto 0) <= ADl;
                      hex_out2 <= "0000110";
     when "01" => A2<= PC;
                      hex_out2 <= "0100100";
     when "10" => A2<= SP;
                      hex_out2 <= "0100000";
     when "11" => A2<= ATMP;
                      hex_out2 <= "0100000";
    end case;
end process;

end Behavioral;