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Apr 24th, 2018
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VHDL 2.06 KB | None | 0 0
  1. module micromachine(rst, clk, areg[4..0], breg[4..0], dreg[4..0], cmd_ual[5..0], oe_num[1..0], write, monitor[31..0], switch[7..0], swClk, ssgClk, pwmClk :
  2. dbus[31..0], N, Z, V, C, ir[31..0], break, leds[7..0], ssegs[7..0], anodes[3..0], pwm_out)
  3.  
  4.  
  5. //Parsage des adresses
  6.     csRam = /abus[31]*/abus[30]*/abus[29]*/abus[28];    //0
  7.     csSw = abus[31]*/abus[30]*/abus[29]*abus[28];       //9
  8.     csSeg = abus[31]*/abus[30]*abus[29]*/abus[28];      //10
  9.     csLd = abus[31]*/abus[30]*abus[29]*abus[28];        //11
  10.     csPwm = abus[31]*abus[30]*/abus[29]*/abus[28];      //12
  11.    
  12.    
  13.  
  14. //Decode de oe_num
  15.     oe_ual = /oe_num[1]*oe_num[0];
  16.     oe_mem = oe_num[1]*/oe_num[0];
  17.     oe_mon = oe_num[1]*oe_num[0];
  18.  
  19.  
  20. //gestion des registres
  21.  
  22.     registres(rst, clk, areg[4..0], breg[4..0], dreg[4..0],dbus[31..0] : abus[31..0], bbus[31..0], ir[31..0], break);
  23.    
  24. //gestion de l'Ual
  25.     ual(abus[31..0], bbus[31..0], cmd_ual[5..0] : sual[31..0], enN, enZ, enVC, dN, dZ, dV, dC);
  26.     dbus[31..0] = sual[31..0] : oe_ual;
  27.    
  28.     //gestion des valeurs de sortie de l'UAL
  29.             N:=dN;  N.clk = clk; N.rst = rst; N.ena = enN;
  30.             Z:=dZ;  Z.clk = clk; Z.rst = rst; Z.ena = enZ;
  31.             V:=dV;  V.clk = clk; V.rst = rst; V.ena = enVC;
  32.             C:=dC;  C.clk = clk; C.rst = rst; C.ena = enVC;
  33.        
  34.    
  35. //gestion de la ram
  36.     rams_asyn_read512x32(clk, writeram, abus[8..0], dbus[31..0] : doutram[31..0]);
  37.     writeram = write*csRam;
  38.     dbus[31..0] = doutram[31..0] : rampassedebus;
  39.     rampassedebus = oe_mem*csRam;
  40.    
  41. //Gestion des switch
  42.     reg8(rst, swClk, 1, switch[7..0] : switchsortie[7..0]);
  43.     //gestion de la sortie des switch
  44.     dbus[7..0] = switchsortie[7..0] : switchdansbus;
  45.     switchdansbus = oe_mem*csSW;
  46.    
  47. //Gestion des leds
  48.     reg8(rst, clk, ecritureLed, dbus[7..0] : leds[7..0]);
  49.     ecritureLed = write*csLd;
  50.    
  51. //gestion de l'afficheur 7 segments
  52.     segs7(rst, clk, ssgClk, ss7en, abus[0], dbus[15..0] :   anodes[3..0], ssegs[7..0]);
  53.     ss7en = write * csSeg;
  54.    
  55. //gestion du module PWN
  56.     pwm_module(rst, clk, pwmClk, enPWN, abus[0], dbus[15..0] : pwm_out);
  57.     enPWN = write * csPwm;
  58.    
  59. //gestion du moniteur
  60.     dbus[31..0] = monitor[31..0] : oe_mon;
  61.    
  62. end module
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