main.c for stm32/example/08-clocking

/**
 * Main code of firmware
 */
#include "stm32f10x.h"
#include "core_cm3.h"
#include "main.h"
void main();
/* Main function */
void main(void) {
        /* setup i/o port c */
        RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
        LED_PORT->CRH &= ~(GPIO_CRH_CNF8 | GPIO_CRH_CNF9);
        LED_PORT->CRH |= GPIO_CRH_CNF8_1 | GPIO_CRH_CNF9_1;
        LED_PORT->CRH |= GPIO_CRH_MODE8_0 | GPIO_CRH_MODE9_0;
        /* setup i/o port a */
        RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN;
        /* setup AFIO andEXTI */
        AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI0_PA;
        EXTI->IMR |= (1 << 0);
        EXTI->FTSR |= (1 << 0);
        /* remap TIM3 to pc6..9 pins port C */
        AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_FULLREMAP;
        /* enable security HSE - CSS */
        RCC->CR |= RCC_CR_CSSON;
        /* setup PLL from HSE */
        /** enable HSE and wait to ready */
        RCC->CR |= RCC_CR_HSEON;
        while ((RCC->CR & RCC_CR_HSERDY) == 0);
        /** setup PLL, enable and wait to ready */
        RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL);
        RCC->CFGR |= (RCC_CFGR_PLLSRC_PREDIV1);
        RCC->CR |= RCC_CR_PLLON;
        while ((RCC->CR & RCC_CR_PLLRDY) == 0);
        /** select PLL for system clock and wait to select */
        RCC->CFGR &= ~RCC_CFGR_SW;
        RCC->CFGR |= RCC_CFGR_SW_PLL;
        while ((RCC->CFGR & RCC_CFGR_SWS_PLL) == 0);
        /* setup TIM3 counter */
        RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
        TIM3->PSC = 8000 - 1;
        TIM3->ARR = 1000;
        /* setup TIM3 compare block */
        /** setup CC3..4 as output */
        TIM3->CCMR2 &= ~(TIM_CCMR2_CC3S | TIM_CCMR2_CC4S);
        /** setup CC3..4 to PWM mode 1 */
        TIM3->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
        /** setup value to compare registers 3..4 */
        TIM3->CCR3 = 0;
        TIM3->CCR4 = 500;
        /** setup channels 3..4 to corresponding output pin */
        TIM3->CCER |= TIM_CCER_CC3E | TIM_CCER_CC4E;
        /* enable TIM3 */
        TIM3->CR1 |= TIM_CR1_CEN;
        /* enable EXTI0 interrupt */
        NVIC_EnableIRQ(EXTI0_IRQn);
        /* infinity loop */
        while (1);
}